Abstract: A light emitting module including a substrate, a first light emitting part disposed on the substrate, and a second light emitting part disposed on the substrate and spaced apart from the first light emitting part by an isolation trench between the first and the second light emitting parts, in which the first light emitting part and the second light emitting part include a first light emitting region and a second light emitting region, respectively, the second light emitting region being spaced apart from the first light emitting region, each of the first and second light emitting parts further includes a wavelength conversion layer covering the first and second light emitting regions, the wavelength conversion layers further include a barrier layer, and the isolation trench and the barrier layer vertically overlap each other on the base substrate.

Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region.

Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.

Abstract: A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Abstract: An image sensor includes a first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each of the pixels include at least one photodiode configured to generate a charge in response to light, and a pixel circuit configured to generate a pixel signal corresponding to the charge. A second layer includes a second logic circuit that is connected to the pixel array and the first logic circuit and is on the first layer. A third layer includes storage elements that are electrically connected to at least one of the pixels or the first logic circuit and an insulating layer on the storage elements. A lower surface of the insulating layer is attached to an upper portion of the first layer, and an upper surface of the insulating layer is attached to a lower portion of the second layer.

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first structure and a second structure. The method further includes replacing the second structure with a third structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first structure and the second sacrificial layers in the third structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first structure and each of the second semiconductor layers in the third structure, respectively.

Abstract: A manufacturing method of a protective film agent for laser dicing that includes a solution preparation step of preparing a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed; and an ion-exchange treatment step of carrying out ion exchange of sodium ions in the solution by using a cation-exchange resin.

Abstract: A display device includes a second transparent display panel overlapping the first transparent display panel and including a plurality of pixels. The display device further includes an elastic member pressing one side of the second transparent display panel. The display device further includes an adjustment member at the other side of the second transparent display panel and moving the second transparent display panel to left side or right side. Therefore, there is provided a display device capable of both of a transparent double-sided display and a general double-sided display.

Abstract: In some embodiments, a semiconductor structure includes: a first region comprising a first epitaxial oxide material; a second region comprising a second epitaxial oxide material; and a chirp layer located between the first and the second regions. The chirp layer can include alternating layers of a plurality of wide bandgap epitaxial oxide material layers (WBG layers) and a plurality of narrow bandgap epitaxial oxide material layers (NBG layers), wherein thicknesses of the NBG layers and the WBG layers change throughout the chirp layer. The WBG layer can comprise (Alx1Ga1?x1)y1Oz1, wherein x1 is from 0 to 1, wherein y1 is from 1 to 3, and wherein z1 is from 2 to 4. The NBG layer can comprise (Alx2Ga1x?2)y2Oz2, wherein x2 is from 0 to 1, wherein y2 is from 1 to 3, and wherein z2 is from 2 to 4, and wherein x1 and x2 are different from one another.

Abstract: A light emitting device including a first light emitting part having a first area, a second light emitting part having a second area, and a third light emitting part having a third area, in which the first light emitting part is disposed on the same plane as the second light emitting part, the third light emitting part is disposed over the first and second light emitting parts, and the third area is larger than each of the first and second areas.

Abstract: A display apparatus includes an oxide semiconductor pattern disposed on a device substrate and including a channel region disposed between a source region and a drain region, a gate electrode overlapping the channel region of the oxide semiconductor pattern and having a structure in which a first hydrogen barrier layer and a gate conductive layer are stacked, and a gate insulating film disposed between the oxide semiconductor pattern and the gate electrode to expose the source region and the drain region of the oxide semiconductor pattern. The gate electrode exposes a portion of the gate insulating film that is adjacent to the source region and a portion of the gate insulating film that is adjacent to the drain region.

Abstract: A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface.

Abstract: A display device includes a substrate including a display area at which an image is displayed and a non-display area which is adjacent to the display area, and in the non-display area a common voltage transmitting line which is connected to the display area and through which a common voltage is provided to the display area, an organic insulating layer between the common voltage transmitting line and the substrate, a first opening which is in the common voltage transmitting line and exposes the organic insulating layer to outside the common voltage transmitting line and an auxiliary electrode which faces the organic insulating layer with the common voltage transmitting line therebetween, contacts the common voltage transmitting line at the first opening and covers the first opening.

Abstract: A semiconductor component, in particular for a varactor, having at least one first semiconductor layer and a second semiconductor layer. At least two identical surface electrodes are arranged directly or indirectly on the second semiconductor layer facing away from the first semiconductor layer in order to form two anti-serially connected diodes. The surface electrodes are arranged in an interacting manner such that a load carrier zone which forms the common counter electrode for the surface electrodes is arranged in the first semiconductor layer at least in the operating state, and at least one control contact for controlling the potential of the load carrier zone is provided in a region of the load carrier zone on the second semiconductor layer face facing away from the first semiconductor layer.

Abstract: A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

Abstract: A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.