Patents Examined by Khaja Ahmad
  • Patent number: 11764204
    Abstract: Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: September 19, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Ralph D. Moore, Franklin M. Murden, Peter Delos, Srivatsan Parthasarathy, Javier Salcedo, John Guido
  • Patent number: 11757017
    Abstract: After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n? buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n? buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n? buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 12, 2023
    Assignee: PAKAL TECHNOLOGIES, INC
    Inventors: Paul M Moore, Vladimir Rodov, Richard A Blanchard
  • Patent number: 11749544
    Abstract: A process condition measurement wafer assembly is disclosed. In embodiments, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top substrate and bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In embodiments, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse voltage potentials across the bottom substrate and the top substrate.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: September 5, 2023
    Assignee: KLA Corporation
    Inventors: Farhat A. Quli, Andrew Nguyen, James Richard Bella
  • Patent number: 11742381
    Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 29, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Gordon M. Grivna, Yusheng Lin
  • Patent number: 11742254
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11742422
    Abstract: A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: August 29, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Lun Tu, Shyi-Yuan Wu
  • Patent number: 11735419
    Abstract: A method for protecting a semiconductor film comprised of one or more layers during processing. The method includes placing a surface of the semiconductor film in direct contact with a surface of a protective covering, such as a separate substrate piece, that forms an airtight or hermetic seal with the surface of the semiconductor film, so as to reduce material degradation and evaporation in the semiconductor film. The method includes processing the semiconductor film under some conditions, such as a thermal annealing and/or controlled ambient, which might cause the semiconductor film's evaporation or degradation without the protective covering.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 22, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Christian J. Zollner, Michael Iza, James S. Speck, Shuji Nakamura, Steven P. DenBaars
  • Patent number: 11716872
    Abstract: The present disclosure provides a display device and a method for manufacturing the same. The display device includes a display substrate; a first cover plate on a side of the display substrate; at least one support layer on a side of the first cover plate distal to the display substrate. The support layer includes a support structure and a second cover plate. The second cover plate is on a side of the first cover plate distal to the display substrate, and the support structure is configured to support the second cover plate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 1, 2023
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhuyi Li, Qi Liu, Zihua Li, Qiang Wang
  • Patent number: 11711924
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 11705499
    Abstract: The present application discloses a semiconductor device with an inverter and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; a first impurity region and a second impurity region respectively positioned on two sides of the gate structure and positioned in the substrate; a first contact positioned on the first impurity region and including a first resistance; a second contact positioned on the first impurity region and including a second resistance less than the first resistance of the first contact. The first contact is configured to electrically couple to a power supply and the second contact is configured to electrically couple to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact, and the second contact together configure an inverter.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: July 18, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Chi Lai
  • Patent number: 11700741
    Abstract: A display device includes: a display panel; a metal layer disposed on one surface of the display panel and including a first bending portion, and a first flat portion and a second flat portion disposed with the first bending portion interposed therebetween; a first adhesive layer including a first extended portion and a second extended portion disposed along the edge of the first flat portion of the metal layer; and a second adhesive layer disposed along the edge of the second flat portion of the metal layer, wherein the metal layer includes an exposed region in which the first adhesive layer and the second adhesive layer are not disposed, and the exposed region is disposed between the first extended portion and the second extended portion in the first flat portion.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun Jae Kim, Jae Chun Park, Sang Wol Lee, Mun Sik Ham
  • Patent number: 11699745
    Abstract: A thyristor includes a first transistor and a second transistor. The first transistor has a first end serving as an anode end. The second transistor has a control end coupled to a second end of the first transistor, a first end coupled to a control end of the first transistor, and a second end coupled to the first end of the second transistor and serving as a cathode end.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: July 11, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Wen-Tsung Huang, Chih-Wei Hsu
  • Patent number: 11700755
    Abstract: Provided is an organic light emitting display device. The organic light emitting display device includes a substrate including an active area and an inactive area at least partially surrounding the active area, an organic light emitting element in the active area, and a conductive line disposed to have a vertically uneven shape in the inactive area and provided to transmit power to the organic light emitting element. The conductive line covers an area including at least one or more grooves in which an inorganic layer is dug.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 11, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Taehwi Kim, Hyunseok Hong, MinJi Kang
  • Patent number: 11694928
    Abstract: According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 4, 2023
    Assignee: Kioxia Corporation
    Inventor: Mika Fujii
  • Patent number: 11688739
    Abstract: There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 27, 2023
    Assignee: PIXART IMAGING INC.
    Inventors: Yung-Ju Wen, Han-Chi Liu, Hsin-You Ko
  • Patent number: 11688836
    Abstract: A light emitting module including a substrate, a first light emitting part disposed on the substrate, and a second light emitting part disposed on the substrate and spaced apart from the first light emitting part by an isolation trench between the first and the second light emitting parts, in which the first light emitting part and the second light emitting part include a first light emitting region and a second light emitting region, respectively, the second light emitting region being spaced apart from the first light emitting region, each of the first and second light emitting parts further includes a wavelength conversion layer covering the first and second light emitting regions, the wavelength conversion layers further include a barrier layer, and the isolation trench and the barrier layer vertically overlap each other on the base substrate.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: June 27, 2023
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jong Min Lee, Bang Hyun Kim, Jae Ho Lee
  • Patent number: 11682719
    Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: June 20, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kato, Tatsunori Sakano
  • Patent number: 11683941
    Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari, Takashi Ando
  • Patent number: 11676871
    Abstract: A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 13, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasutaka Shimizu
  • Patent number: 11664426
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang