Abstract: Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an equalize circuit to equalize a pair of internal nodes to a prescribed potential, a transfer gate circuit activated, when the equalize circuit completes equalization, to couple the pair of first signal lines and the pair of internal nodes, an amplifier circuit to differentially amplify the signals on the internal nodes when the transfer gate completes the transfer operation, an output transfer circuit to transmit the signals on the pair of internal nodes onto the pair of second signal lines in synchronization with the clock signal, and a control circuit to control the operation of the equalize circuit, the transfer gate circuit and the amplifier circuit. After the pair of internal nodes is equalized to the prescribed potential, the signals from the pair of first signal lines are received and amplified.

Abstract: A carrier phase follower is provided that can follow the carrier phase even when the carrier phase angle varies with respect to a reference frequency signal. Demodulation data is decided, without any carrier regeneration, based on the signal by obtained demodulating a digital-modulated signal with a reference frequency signal while following the carrier phase with respect to the reference frequency signal. The carrier phase follower includes the phase angle decision unit 13 which decides the shift of an offset phase angle as well as the digital filter 14 and the cumulative adder 12 which update a set offset phase angle based on the shift. Specifically, the phase angle decision unit 13 corrects the phase angle of a demodulated signal from the phase angle calculation unit 8 according to the set offset phase angle from the cumulative adder 12, with the decision timing synchronized with the symbol of the digital-modulated signal, to decide the shift of the offset phase angle.

Abstract: A method of detecting a frequency of a digital phase locked loop in an optical disc reproduction and/or recording apparatus, which includes (a) detecting an edge point of an input signal, (b) sampling a previous and following input signal on the basis of the detected edge point into a predetermined frequency, (c) counting a number of reference clock signals between the detected edge point and a sample which is positioned previously, adding a count value and an interval of time corresponding to the count value to obtain a frequency count value at the edge point, and (e) comparing the obtained frequency count value with a predetermined reference value, to enhance the frequency according to the comparison result can detect frequency having high resolution with only a reference clock frequency without heightening a frequency of a reference clock signal, to thereby enhance the quality of data.

Abstract: A phase detector for a clock and data recovery circuit from random non-return-to zero (NRZ) data signal includes a plurality (e.g., preferably three) edge-triggered flip-flops. The incoming NRZ data are sampled by a pair of edge-triggered flip-flops using the transition of the clock generated by the clock recovery circuit. A third edge-triggered flip-flop processes the outputs from the edge-triggered flip-flop pair to indicate whether the generated clock leads or lags the received data.

Abstract: A data transmission system employs an iterative decoder that applies decision feedback equalization (DFE) to channel output samples of a packet of data. The iterative decoder receives a stream of channel output samples as packets that may, for example, be read from a sector of a recording medium. Each packet may represent user data encoded, for example, with a concatenated code formed from N component codes, N a positive integer. The iterative decoder employs I decoding iterations, I a positive integer. DFE employs two filters: a feedforward filter and a feedback filter. The feedforward filter, which may be a whitened-matched filter used for detection, shifts dispersed channel output energy into the current sample. The feedback filter cancels energy of trailing inter-symbol interference from previous symbols.

Abstract: An apparatus including a switched voltage bit cell (SVBC) array to receive an input voltage signal, each bit cell of the SVBC array configured to add a voltage to the input voltage signal and a delay locked-loop configured to delay an output voltage signal of each bit cell of the SVBC array by a determined step.

Abstract: A receiver and a phase extraction circuit are capable of demodulating at high resolution if the sampling frequency is close to the frequency of received signal. In the phase extraction circuit, the received signal modulated in phase is sampled when lowered to an intermediate frequency. When the sampling frequency at this time is selected around the intermediate frequency, a continuous portion appears in one position of the sampling data row. The position of the continuous portion is determined by the phase of the received signal, and therefore a one-to-one correspondence table of the continuous position and phase of received signal is prepared. By detecting the continuous position, the phase information can be obtained from the table. As a result, it is possible to demodulate directly at the intermediate frequency, and therefore the circuit scale is substantially simplified, the number of parts is curtailed, and the size is reduced.

Abstract: A novel receiver having a decision feedback equalizer is disclosed. The decision feedback equalizer is equipped with a feedback section to generate a feedback signal. The feedback section includes a plurality of taps to successively delay a filtered version of an input signal of the decision feedback equalizer. The feedback section further includes a plurality of comparators, correspondingly coupled to the taps, to examine the corresponding delayed versions of the filtered input signal to affect the generation of the feedback signal with the examination results. In one embodiment, the novel receiver is employed in a network interface controller. In yet another embodiment, the novel network interface controller is employed in a computer system.

Abstract: A method and apparatus are disclosed for determining the data rate of a received signal in a communication system utilizing code division multiple access (CDMA) techniques. The well-known Viterbi decoding-based rate detection approach is combined with the conventional repetition pattern-based rate detection approach. The hybrid approach possesses the advantages of both prior approaches, without their disadvantages. The computationally efficient repetition pattern-based data rate detection approach, while not as reliable as the Viterbi decoder-based data rate detection approach, provides reliable data rate detection most of the time. The repetition-pattern data rate detection approach is used as long as a predefined reliability metric is satisfied, and only uses the more computationally intensive Viterbi decoder-based data rate detection approach when detection reliability may be compromised.

Abstract: A system and method facilitate estimating noise in a received signal. The received signal includes a plurality of data tones. Noise is estimated for a selected subset of data tones for each data burst, such that noise estimates for all data tones can be computed over a plurality of data bursts. As a result of spreading the noise estimates over more than one burst, the overall computations associated with obtaining the noise estimates can be reduced based on the size of the respective subsets. The updated data tone noise estimates further can be employed in subsequent processing, such as in beamforming calculations.

Abstract: A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of a wire line pair (20) includes an interface (212, 292) to the wire line pair (20) and a signal converter (214, 290) with a terminal coupled to the interface. An on/off-hook detector(300) drives an impedance analyzer function (304) that is able to measure transmission line parameters based on the current line characteristics of the wire line pair (20). A control logic block (310) performs the actions required to adapt to a new line conditions of the wire line pair (20) and rapidly adapt to the new on/off hook condition.

Abstract: A communications receiver includes an analog input for receiving an analog signal having a time-varying DC voltage drift. A variable gain amplifier is coupled to the analog input and is adapted to amplify the analog signal based on a gain set by a gain control input to the amplifier. An analog-to-digital (A/D) converter is coupled to an output of the amplifier and is adapted to convert the amplified analog signal to a series of digital values. A drift estimator is coupled to the A/D converter, which generates an estimate of the time-varying DC voltage drift based on the series of digital values. A gain adjuster is coupled between the drift estimator and the amplifier, which adjusts the gain control input based on the drift estimate.

Abstract: In a frequency adjusting circuit, an oscillator outputs cosine and sine waves. A quadrature demodulator extracts and outputs the baseband signal of an in-phase component from a carrier wave input from an antenna using the cosine wave and the baseband signal of a quadrature component from the carrier wave using the sine wave. First and second A/D converters convert the baseband signals into digital signals. First and second despreaders despread the digital signals. A frequency error detection section detects the error between the frequency of the carrier wave and the frequency of the cosine and sine waves from the values of the signals output from the despreaders. A reference oscillator outputs the value of an oscillation frequency as the frequency of the cosine and sine waves and changes the value of the oscillation frequency to cancel the detected frequency error.

Abstract: A system to analyze and compensate for noise on a transmission line (35) is provided. The system comprises a transmission card which includes a transceiver (32), and a microprocessor (34) attached to the transceiver (32). The system also comprises a transmission line (35) coupled to the transceiver (32) and at least one customer premise equipment (38) coupled to the transceiver (32) by the transmission line (35). The microprocessor (34) is operable to monitor the transmission line (32) and determine the signal-to-noise ratio on the line as a function of frequency, and adjust the rate of transmission in terms of bandwidth in terms of bits as a function of frequency.

Abstract: An interpolating bandpass filter for packet-data receiver synchronization comprises a single delay line that delays the passband-sampled data from the analog-to-digital converter, and a convolving structure that uses the delay line to implement a L-times oversampling bandpass filter. A separate accumulator accumulates a fractional phase difference that represents the frequency offset between the remote transmitter's frequency and the receiver's sampling frequency. The integer portion of the accumulator is used to determine the number of samples to delay the input of the filter, while the fractional portion is used to choose two coefficient sets closest to the desired delay and to interpolate between these two filter sets.

Abstract: A method (32) of operating a spread spectrum communications receiver (20). The method demodulates a current path group with a demodulator (28), wherein the current path group comprises one or more current paths and wherein the demodulating step comprises demodulating the one or more current paths with a respective one more demodulation elements. The method also determines (42) one or more survey groups at the receiver, wherein each survey group comprises of a unique combination of one or more new paths and zero or more current paths. Still further, the method determines a quality measure (52) of the current path group and (53) of one or more survey groups. Further, the method selectively assigns (62) a selected one of the survey groups to respective elements of the demodulator in place of the current path group in response to a comparison of the quality measure of the selected one of the survey groups with the quality measure of the current path group.

Abstract: Transmission of coded signals of different types in a system comprising a plurality of operative telecommunication stations is described. The system allows transmission of different type of signals in their coded form towards a receiving end of the transmission path and ensures that the signals are decoded into their decompressed digital form only in the last operative decoder along the transmission path. Signal classification messages are transmitted along the transmission path and allow operating the system in an environment of various types of signals.

Abstract: A system for transmitting, receiving, recovering, and reproducing digitized samples of analog signals while concealing unrecoverable digitized samples of analog signals to maintain a level of fidelity in reproducing the analog signals. The digitized samples of the analog signals are burst transmitted such that the probability of interference with the transmission and thus corruption of the digitized samples of the analog signals is minimized. The digitized samples are received without synchronizing a receiving clock with a transmitting clock to capture the digitized samples of the analog signals. The digitized samples are converted from various sampling rates to digitized samples of the analog signals having a rate. Any large groups of digitized samples that are in error or corrupted in transmission are softly muted to avoid annoying clicks.

Abstract: A system and method are disclosed for transmitting data over multiple twisted pairs and receiving the data at a single receiver. In one embodiment, data is transmitted over an additional channel existing as the difference between the average voltages of two twisted pairs.

Abstract: In a direct conversion receiving apparatus, a first frequency converting section includes a first capacitor, and frequency-converts a high frequency reception signal into a first base band signal using a first local oscillation frequency signal. Then, the; first frequency converting section removes a DC component from the first base band signal using the first capacitor, and converts the first base band signal with the DC component removed into a first digital signal. A second frequency converting section includes a second capacitor, and frequency-converts the high frequency reception signal into a second base band signal using a second local oscillation frequency signal which is different from the first local oscillation frequency signal by 90 degrees in phase. Then, the second frequency converting section removes a DC component from the second base band signal, using the second capacitor, and converts the second base band signal with the DC component removed into a second digital signal.