Patents Examined by Khanh Dang
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Patent number: 9460038Abstract: Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals.Type: GrantFiled: November 17, 2011Date of Patent: October 4, 2016Assignee: VIA TECHNOLOGIES, INC.Inventor: Darius D. Gaskins
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Patent number: 9454502Abstract: Provided are a parallel communication device and a communication method thereof. The parallel communication device includes: a first receiving terminal receiving communication data transmitted through a master device; a first transmitting terminal transmitting the communication data received through the first receiving terminal to a slave device; a switch managing a communication line disposed between the first transmitting terminal and a plurality of slave devise; and a control unit confirming a first slave device to which the communication data are to be transmitted by using destination information in the communication data, and transmitting the received communication data to the confirmed first slave device.Type: GrantFiled: June 7, 2012Date of Patent: September 27, 2016Assignee: LSIS CO., LTD.Inventor: Tae Bum Park
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Patent number: 9436647Abstract: A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.Type: GrantFiled: September 13, 2013Date of Patent: September 6, 2016Assignee: STMicroelectronics Asia Pacific Pte LtdInventors: Nee Loong Wilson Low, Chaochao Zhang
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Patent number: 9430438Abstract: A two wire bidirectional bus system is provided in which at least one of the slave nodes is configured to enter into a sleep mode, thereby minimizing power drainage, whenever the bus master stops transferring data over the bidirectional bus, and to wake up whenever the bus master begins to transfer data over the bidirectional bus.Type: GrantFiled: March 8, 2014Date of Patent: August 30, 2016Assignee: ATIEVA, INC.Inventor: Richard J. Biskup
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Patent number: 9424214Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.Type: GrantFiled: September 22, 2013Date of Patent: August 23, 2016Assignee: Mellanox Technologies Ltd.Inventors: Diego Crupnicoff, Todd Wilde, Richard Graham, Michael Kagan
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Patent number: 9411766Abstract: Single Optical Fiber KVM (Keyboard Video Mouse) systems are provided that comprises of two subsystems: an electro-optical transmitter subsystem and an electro-optical receiver subsystem. The single optical fiber KVM is configured to support all required bi-directional communications.Type: GrantFiled: September 6, 2012Date of Patent: August 9, 2016Assignee: HIGH SEC LABS INC.Inventor: Aviv Soffer
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Patent number: 9405566Abstract: Methods and systems for improved access to storage resources include installing a virtual storage appliance as a virtual machine on a hypervisor. The virtual storage appliance installs itself as a virtual PCI-E device and communicates with guest operating systems of the hypervisor using direct memory access via a PCI-E non-transparent bridge. The storage virtual appliance provides access to local and external storage resources with very high performance to applications running under the guest operating system, thereby overcoming performance barriers associated with native hypervisor driver models.Type: GrantFiled: May 24, 2013Date of Patent: August 2, 2016Assignee: Dell Products L.P.Inventors: Gaurav Chawla, Michael Karl Molloy, Robert Wayne Hormuth
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Patent number: 9400758Abstract: The present invention relates to a reset method and a network device. The method includes: receiving, by an SPI Flash, a reset instruction sent by a processor; and performing reset processing corresponding to the reset instruction according to the reset instruction, where the reset instruction includes interrupting a current operation, recording interruption state information when the current operation is interrupted, and setting a current state to a state of responding to a read instruction of the processor; after finishing the reset operation, sending, by the processor, a read instruction to the SPI Flash, and receiving interruption state information sent by the SPI Flash according to the read instruction; and then determining, according to the interruption state information, whether the interrupted operation in the SPI Flash needs to be continued, and if yes, sending an instruction of continuing the interrupted operation to the SPI Flash.Type: GrantFiled: November 5, 2013Date of Patent: July 26, 2016Assignee: Huawei Technologies Co., Ltd.Inventors: Kuichao Song, Junyang Rao, Qiang Liu
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Patent number: 9360913Abstract: A method of providing a clock frequency to a processor is described. The method in accordance with the invention comprises the step of providing at least one reference signal and the step of determining a control value which relates to a desired first frequency. A second signal that relates to the control value is then used in a subsequent step as an input signal for a noise shaper. Then, a first signal which has the first frequency is generated by combining the output of the noise shaper with one of the at least one reference signals. The first signal is used as a clock frequency of the processor. In a preferred embodiment, one reference signal with a fixed reference frequency is provided. The reference signal is gated or enabled and hold by the output signal provided by a 1-bit noise shaper, whereby the first frequency is generated which is then used as processor clock frequency.Type: GrantFiled: June 6, 2007Date of Patent: June 7, 2016Assignee: NXP B.V.Inventor: Steven Aerts
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Patent number: 9355050Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.Type: GrantFiled: November 5, 2013Date of Patent: May 31, 2016Assignee: QUALCOMM IncorporatedInventors: Thomas Zeng, Samar Asbe, Azzedine Touzni
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Patent number: 9342377Abstract: Controlling access to a resource by a plurality of resource requesters is disclosed. The resource lock operates in a contention efficient (heavyweight) operating mode, and in response to a request from a resource requester to acquire the resource lock, a count of a total number of acquisitions of the resource lock in the contention efficient operating mode is incremented. In response to access to the resource not being contended by more than one resource requester, a count of a number of uncontended acquisitions of the resource lock in the contention efficient operating mode is incremented, and a contention rate is calculated as the number of uncontended acquisitions in the contention efficient operating mode divided by the total number of acquisitions in the contention efficient operating mode. In response to the contention rate meeting a threshold contention rate, the resource lock is changed to a non-contention efficient (lightweight) operating mode.Type: GrantFiled: March 13, 2012Date of Patent: May 17, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: David K. Siegwart
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Patent number: 9336029Abstract: A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry.Type: GrantFiled: August 4, 2010Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric N. Lais, Steve Thurber
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Patent number: 9330047Abstract: In one example, a method includes receiving, from a user application and with a wireless docking service of a wireless docking communications stack executing on a computing device, a request to discover one or more peripheral functions within wireless communication range of the computing device. The method also includes, responsive to receiving the request, discovering, with the wireless docking service, the one or more peripheral functions without communicating with a wireless docking center. The method further includes consolidating the peripheral functions into a docking session for the user application. The method also includes, responsive to receiving the request, sending a docking session identifier and one or more respective references corresponding to the one or more peripheral functions to the user application.Type: GrantFiled: September 6, 2013Date of Patent: May 3, 2016Assignee: QUALCOMM IncorporatedInventors: Xiaolong Huang, Phanikumar Kanakadurga Bhamidipati, Vijayalakshmi Rajasundaram Raveendran, Rolf De Vegt
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Patent number: 9330045Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device is disclosed. The CAN device includes a TXD input interface, a TXD output interface, an RXD input interface, an RXD output interface, and a traffic control system connected between the TXD input and output interfaces and between the RXD input and output interfaces. The traffic control system is configured to detect the presence of CAN Flexible Data-rate (FD) traffic on the RXD input interface and if the traffic control system detects the presence of CAN FD traffic on the RXD input interface, disconnect the RXD input interface from the RXD output interface and disconnect the TXD input interface from the TXD output interface.Type: GrantFiled: April 30, 2014Date of Patent: May 3, 2016Assignee: NXP B.V.Inventors: Matthias Muth, Bernd Elend
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Patent number: 9330049Abstract: Embodiments of the present invention provide a method and apparatuses for monitoring a system bus. The method includes: performing, by a monitoring apparatus, real-time monitoring on a corresponding system bus, and when detecting that a command is transmitted through the system bus, obtaining command information; determining, according to the command information, whether a command transmission exception occurs in the system bus; if no command transmission exception occurs in the system bus, when detecting that data corresponding to the command is transmitted through the system bus, determining, according to the data and the amount of the data, whether a command exception occurs in the system bus; and when detecting that a response message corresponding to the command is transmitted through the system bus, obtaining a command wait time of the command, and determining, according to the command wait time, whether a timeout exception occurs in the system bus.Type: GrantFiled: April 17, 2013Date of Patent: May 3, 2016Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qiang Fu, Xiping Zhou
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Patent number: 9311208Abstract: Technologies are described herein for generating field replaceable unit (FRU) information files in a format that is readable by a management controller in accordance with IPMI such that the FRU and the management controller are interoperable. In particular, a FRU installation station is in operative communication with a general purpose computer comprising a FRU information conversion module. A script utilized by the FRU information conversion module is configured to receive FRU information relating to a specified FRU and convert the information FRU binary files or a FRU image binary. The FRU binary files or FRU image binary are then received by the FRU installation station where they are subsequently transmitted to the inventory device of the specified FRU storage space according to the specified IPMI standard.Type: GrantFiled: August 9, 2013Date of Patent: April 12, 2016Assignee: AMERICAN MEGATRENDS, INC.Inventor: Jason Andrew Messer
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Patent number: 9311260Abstract: A microarchitecture can be configured to allow a thread's speculative state to be stored when the thread is preempted. The stored speculative state can then be loaded back into the microarchitecture when the thread is resumed to thereby enable the thread to resume execution at the speculative state that existed when the thread was preempted. By maintaining the speculative state of threads, a greater amount of parallel processing is achieved.Type: GrantFiled: December 9, 2013Date of Patent: April 12, 2016Inventor: Jack Mason
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Patent number: 9298653Abstract: A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.Type: GrantFiled: January 29, 2014Date of Patent: March 29, 2016Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Sheng-Yu Peng, Chi-An Lai, Chiang-Hsi Lee, Tzu-Yun Wang
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Patent number: 9285855Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.Type: GrantFiled: August 12, 2011Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Justin Song, Qian Diao
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Patent number: 9280191Abstract: Systems and methods are disclosed that may be used for controlling information handling system power supply based on current system power policy such as current system load power need and/or based on current system load power capping information. The disclosed systems and methods may be so implemented to improve power use efficiency for information handling system applications in which a power supply unit (PSU) has a power delivery capability that is overprovisioned relative to the power-consuming system load component/s of an information handling system.Type: GrantFiled: January 21, 2013Date of Patent: March 8, 2016Assignee: Dell Products LP.Inventors: Johan Rahardjo, Girish Das