Abstract: A communications network is used to couple weld controllers and different operator interface units together, regardless of their data structures. An arbitration system provides a means for one operator interface unit to communicate to a selected weld controller at a given period of time. The operator interface units have one of three modes of operation. These include database master, primary master, and secondary master. During setup of the communications network, the master devices are assigned a physical address that defines the its type and priority within the network. The database master is the only device which can automatically download data to a weld controller. It has the highest priority as a network arbiter. The primary master will act as the network abitrator in the absence of a database master. A secondary master must listen for an access grant from the current network arbiter, before initiating a message packet on the network.

Abstract: A compressed file produced by a server is used for updating a hypertext markup language (HTML) document cached on a client computer with changes so that it is identical to a changed HTML document stored on a server computer. Typically, when a user requests access to the HTML document on a server computer corresponding to the cached HTML document on the client computer, the cached HTML document is opened and processed by a client agent software module to produce a macro name file and a macro definition file. A checksum or macro name is determined for each construct or list in the cached HTML file. Each macro definition in the macro definition file is a concise content of the construct or list comprising a different portion of the HTML file. The client agent transmits the uniform resource locator (URL) for the site from which the cached HTML document was obtained and appends the macro name file (assuming that the server computer hasn't already generated the macro name file).

Abstract: An email mapper to identify sender's U.S. postal address by detecting in the sender's email address, email message, or the sender's posting whether the sender's name and address are identifiable in the signature line of the sender's email and searching one or more electronic white pages to identify the sender's name and postal address. Wherein if no signature line is detected in the sender's email further filtering the sender's email to identify the geographic locale of the sender and then searching against one or more electronic datases, such as a business database, an ISP database, an electronic whitepage, or email mapper's generated relational database, to identify and generate a list of one or more USPS addresses associated with the sender's email address, name and locale of the sender.

Abstract: An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller.

Abstract: A communications system facilitates transactions between a sender and a plurality of recipients as part of an electronic messaging system. Messaging means enable a sender to form an electronic template containing a message in the form of a structured response object for a recipient as part of a transaction between a sender and a recipient(s). Controller means receive and store the message in a virtual mailbox assigned to the transaction for access by the sender and the recipient(s). The controller means generate and send to the recipients an indicator or pointer identifying the message at an address for the virtual mailbox. The recipient(s) use the pointer address to view the electronic message in the form of a structured object response at the virtual mailbox in the controller. The recipient may ignore or file the message or send a response to the virtual mailbox. The response or lack of response to the structured object response by the recipient (s) is tracked and recorded by the controller.

Abstract: A method of operating a microprocessor (12) having an on-chip storage resource (100a). The method first receives a data fetching instruction into an instruction pipeline (38) at a first time. The instruction pipeline has a preliminary stage (40), a plurality of stages (42 through 46) following the preliminary stage, and an execution stage (48) following the plurality of stages. The step of receiving a data fetching instruction at the first time comprises receiving the data fetching instruction in the preliminary stage. The method second performs various steps, including fetching a first data quantity (MRU TARGET DATA) for the data fetching instruction to complete the execution stage of the pipeline, completing the execution stage in connection with the data fetching instruction using the first data quantity, and storing the first data quantity in the on-chip storage resource. The method third receives the data fetching instruction into the preliminary stage at a second time (108).

Abstract: A communication system which includes more efficient packet conversion and routing for improved performance and simplified operation. The communication system includes one or more inputs for receiving packet data and one or more outputs for providing packet data. In one embodiment, the present invention comprises a "traffic circle" architecture for routing packet data and converting between different packet formats. In this embodiment, the system includes a data bus configured in a ring or circle. A plurality of port adapters or protocol processors are coupled to the ring data bus or communication circle. Each of the port adapters are configurable for converting between different types of communication packet formats. In the preferred embodiment, each of the port adapters are operable to convert between one or more communication packet formats to/from a generic packet format.

Abstract: A memory control circuit in a CD-ROM driving system is provided which controls the writing and reading of data to and from a memory in accordance with a plurality of data operations. The circuit contains a plurality of requesters, a priority level determiner, and a memory control signal generator. The requesters correspond to the plurality of data operations and respectively generate request signals. Furthermore, the requesters respectively generate physical addresses of the memory which are respectively accessed during the data operations. The priority level determiner determines the priority levels of the request signals and outputs a selection signal based on the request signals and the priority levels. Moreover, the selection signal identifies one of the data operations as a selected data operation. The memory control signal generator generates a memory control signal and a memory address which corresponds to one of the physical addresses to be accessed during the selected data operation.

Abstract: A computer-based method of innovatively solving one or more problems using a group assembled at a computerized meeting. One participant of the group is the client who is the owner of or is responsible for the problem or opportunity to be resolved. Each participant is provided with a computer which is networked with all other computers. A group list is created of all the participants of the group, and one participant is designated the facilitator who controls the problem solving process of the meeting. The remaining participants are designated as resources. An agenda is created consisting of placeholders and activities. The resources enter creative springboards into their computers based on the problem to be solved, and these springboards are distributed to all participants. Builds and elaborations are generated by the resources based on the springboards and distributed to all participants.

Abstract: A microchip has a register file having a plurality of registers and an accumulator register connected in parallel with the register file that allow write operations to be performed concurrently during a single write cycle. Write operations can include write data to be written to a destination register and identification data designating a destination register. Where a first instruction designates a register in a register file and second instruction designates an accumulator register, write data from the first and second instructions can be written concurrently to the register file and the accumulator register during a single write cycle. By providing an accumulator register that is separate from the register file, data directed toward an accumulator register is diverted away from the register file and delays in performing write operations to the register file are reduced.