Patents Examined by Khiem D Nguyen
  • Patent number: 11901335
    Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 13, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
  • Patent number: 11901867
    Abstract: A differential amplifier circuit includes a first and second amplifiers that output a differential signal in a radio-frequency band, a first inductor having a first end connected to an output end of the first amplifier, a second inductor having a first end connected to an output end of the second amplifier, a choke inductor connected to second ends of the first and second inductors, a first and second capacitors, and a switch that connects the second capacitor in parallel to the first capacitor or terminates a parallel connection of the first and second capacitors. A resonant circuit formed by connecting the first or second inductor in series with the first capacitor has a different resonant frequency from a resonant circuit formed by connecting the first or second inductor in series with the parallel-connected first and second capacitors. These resonant frequencies correspond to second harmonic frequencies of the differential signal.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 13, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Jun Enomoto, Fumio Harima, Satoshi Tanaka
  • Patent number: 11901485
    Abstract: An object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. The light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. The pixel is electrically connected to a first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The light-emitting element and the oxide semiconductor layer overlap with each other.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryo Arasawa, Hideaki Shishido
  • Patent number: 11894404
    Abstract: The present disclosure provides an optical structure and a method for fabricating an optical structure, the method includes forming a light detection region in a substrate, forming an isolation structure at surrounding the light detection region, and forming a primary grid over the isolation structure, including forming a metal layer over the isolation structure, forming a first dielectric layer over the metal layer, and partially removing the metal layer and the first dielectric layer with a first mask by patterning, and forming a secondary grid at least partially surrounded by the primary grid laterally.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Hao Chen, Kuo-Yu Wu, Tse-Hua Lu
  • Patent number: 11894811
    Abstract: An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 6, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Taotao Yan, Kerou Wang, Wei Wu
  • Patent number: 11894809
    Abstract: Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: February 6, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Haopei Deng
  • Patent number: 11887907
    Abstract: A semiconductor package includes a semiconductor chip having chip pads on a first surface and having first and second side surfaces opposite to each other and third and fourth side surfaces opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Wonyoung Kim
  • Patent number: 11888046
    Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: January 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li
  • Patent number: 11881826
    Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: January 23, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: David P. Singleton, Andrew J. Howlett, John B. Bowlerwell
  • Patent number: 11881456
    Abstract: A semiconductor package includes; an interposer mounted on a package substrate, a first semiconductor device and a second semiconductor device mounted on the interposer, a molding member including an outer side wall portion covering an outer side surface of the first semiconductor device, and a lower portion covering at least a portion of an upper surface of the interposer, and a capping structure including an outer side wall portion covering the outer side wall portion of the molding member.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: January 23, 2024
    Inventor: Heonwoo Kim
  • Patent number: 11876496
    Abstract: Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala
  • Patent number: 11869875
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 9, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Joon Young Park, Jung Soo Park, Ji Hye Yoon
  • Patent number: 11870398
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: January 9, 2024
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Christopher C. Murphy, Jeffrey A. Dykstra
  • Patent number: 11870396
    Abstract: Techniques are described for using valley detection for supply voltage modulation in power amplifier circuits. Embodiments operate in context of a power amplifier circuit configured to be driven by a supply voltage generated by a supply modulator and to receive an amplitude-modulated (AM) signal at its input. The output of the power amplifier circuit can be fed to a valley detector that can detect a valley level corresponding to the bottom of the envelope of the AM signal. The detected valley level can be fed back to the supply modulator and compared to a constant reference. In response to the comparison, the supply modulator can vary the supply voltage to the power amplifier circuit in a manner that effectively tracking the envelope of the power amplifier circuit's output signal, thereby effectively seeking a flat valley for the output signal's envelope.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 9, 2024
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ahmed Emira, Siavash Yazdi, Kaveh Moazzami
  • Patent number: 11870399
    Abstract: A receiver for cancelling common mode offset and crosstalk that amplifies a voltage difference between an input signal and a reference voltage to generate first and second output signals and an internal signal, that generates the same third and fourth output signals as the first and second output signals, generates average voltage levels of the third and fourth output signals by using first and second switching elements and low pass filters to output the average voltage levels as first and second feedback signals, and cancels a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and that generates a control signal to cancel crosstalk of the internal signal by turning on/off the first and second switching elements connected to the low pass filters.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghwan Hong, Youngsoo Sohn, Jeongdon Ihm, Changhyun Bae, Yoochang Sung
  • Patent number: 11863136
    Abstract: The electronic circuits and semiconductor device having the same are provided. The electronic circuit includes: a first transistor including a first electrode coupled with an input voltage; a second transistor including a first electrode coupled with a second electrode of the first transistor; a first capacitor coupled between the first transistor and the second transistor; a first diode including a first terminal coupled with the first electrode of the first transistor; a second diode including a first terminal coupled with a second terminal of the first diode and a second terminal coupled with a second electrode of the second transistor; a second capacitor coupled between the first transistor and the first diode; and a third capacitor coupled between the first diode and the second transistor.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 2, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Tao Zhang, Yulin Chen, Jihua Li, Wenjie Lin
  • Patent number: 11863129
    Abstract: A bias circuit includes first to sixth transistors and first to fifth resistors. The collector of the fifth transistor is coupled to a node in a path connecting the collector of the fourth transistor and one end of the third resistor. The collector of the sixth transistor Tr6 is coupled to one end of the fifth resistor.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hideyo Yamashiro
  • Patent number: 11863139
    Abstract: An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11863138
    Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: January 2, 2024
    Assignee: Analog Devices, Inc.
    Inventor: Devrim Aksin
  • Patent number: 11862566
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 2, 2024
    Inventors: Jun Hyoung Kim, Young-Jin Kwon, Geun Won Lim