Patents Examined by Khristopher Yodichkas
  • Patent number: 9664536
    Abstract: A calibration system having an actuator with a rotatable shaft and a switch box housing a proximity switch and a calibration mechanism. The calibration mechanism is coupled to the shaft and includes a base, a target carrier, a driver, and an actuating button having a cam. The base includes a locating magnet, and the target carrier includes a primary magnet and a bias magnet polarized in the same direction as the locating magnet. The driver is shiftable between a first position in which the driver engages the target carrier and a second position disengaged from the target carrier. The cam engages the driver and shifts the driver between the first and second positions. Upon rotation of the shaft, the bias magnet automatically moves to a position aligned with the locating magnet when the driver is in the second position.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 30, 2017
    Assignee: General Equipment and Manufacturing Company
    Inventors: Scott Carpenter, Charles C. Bilberry
  • Patent number: 9658281
    Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee
  • Patent number: 9568536
    Abstract: A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 14, 2017
    Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sandeep Kumar Goel, Erik Jan Marinissen
  • Patent number: 9568543
    Abstract: A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 9568525
    Abstract: A configuration and a method for capacitive sensing of the rotatory motion of a rotary member are described. The configuration has four electrodes located in one plane, an analysis unit connected to the electrodes and an electrically conducting coupling surface, which is located at the rotary member opposite to the electrodes. The electrodes comprise a central excitation electrode, surrounded by the other electrodes. The coupling surface is opposite to the surface of the excitation electrode in each rotary position and covers a part of the surface formed by the remaining electrodes and passes over the surface formed by the remaining electrodes during a rotation of the rotary member. The remaining electrodes are formed by two sensor electrodes and a joint reference electrode, whereby at least the joint reference electrode is designed different than the sensor electrodes.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 14, 2017
    Assignee: Techem Energy Services GmbH
    Inventor: Jürgen Reus
  • Patent number: 9562931
    Abstract: Devices and methods for sensing current are described herein. One device (100) includes a base member (102) having a first leg (104, 106) and a second leg (104, 106), the legs (104, 106) defining an angle (108) therebetween, a first magnetic current sensor (110, 112) coupled to the base member (102) and positioned at a first location in a plane bisecting the angle (108), and a second magnetic current sensor (110, 112) coupled to the base member (102) and positioned at a second location in the plane bisecting the angle (108).
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: February 7, 2017
    Assignee: Honeywell International Inc.
    Inventors: Xinhui Mao, Huabin Fang
  • Patent number: 9514665
    Abstract: A test device for a display device including a plurality of demultiplexing switches connected to a plurality of data lines in accordance with the present invention includes: a one-sheet test device configured to include a plurality of control switches connected to the demultiplexing switches through a plurality of wires; and a wire test device configured to transmit wire test signals for detecting defects in the wires to a pad connected to the control switches. The wire test device transmits the wire test signals to the pad to detect defects in first wires of the wires and then detect defects in remaining second wires thereof, and the first wires and the second wires are alternatively disposed below the demultiplexing switches to constitute paths for signals transmitted to the demultiplexing switches.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Sae Lee, Jeong-Geun Yoo
  • Patent number: 9488677
    Abstract: A probe card includes a wiring substrate including an opening portion and a connection pad arranged on an upper face of the wiring substrate located on the periphery of the opening portion, a resin portion formed in the opening portion of the wiring substrate, and the resin portion formed of a material having elasticity, a contact terminal arranged to protrude from the lower face of the resin portion, and wire buried in the resin portion and connecting the contact terminal and the connection pad, wherein the contact terminal is formed of an end part of the wire, and is formed integrally with the wire.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 8, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Ryo Fukasawa, Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Mitsuhiro Aizawa
  • Patent number: 9490032
    Abstract: An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sang-Jin Byeon
  • Patent number: 9476913
    Abstract: A probe card includes a wiring substrate including an opening portion, a first connection pad, and a second connection pad arranged in an opposite area to the first connection pad, a resin portion formed in the opening portion, a first wire buried in the resin portion, in which one end is connected to the first connection pad and other end constitutes a first contact terminal, and a second wire buried in the resin portion, in which one end is connected to the second connection pad and other end constitutes a second contact terminal, wherein the first and second wires extend on one line, and the first and second contact terminals are arranged on the one line, and the first and second contact terminals are gathered to be separated such that the first and second contact terminals touch one electrode pad of a text object with a pair.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 25, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Ryo Fukasawa, Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Mitsuhiro Aizawa
  • Patent number: 9470718
    Abstract: A probe card, includes, a wiring substrate having an opening portion and including a first connection pad and a second connection pad, the first connection pad being arranged at a periphery of the opening portion, the second connection pad being arranged to be adjacent to the first connection pad, a resin portion formed inside the opening portion of the wiring substrate, a first wire buried in the resin portion and having one end connected to the first connection pad and the other end constituting a first contact terminal protruding from a lower face of the resin portion, and a second wire buried in the resin portion and having one end connected to the second connection pad and the other end constituting a second contact terminal protruding from a lower face of the resin portion.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 18, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Ryo Fukasawa, Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Mitsuhiro Aizawa
  • Patent number: 9472131
    Abstract: A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: October 18, 2016
    Assignee: Apple Inc.
    Inventors: Mir B. Ghaderi, Shafiq M. Jamal, Sang Y. Youn
  • Patent number: 9459289
    Abstract: A probe card includes a frame-shaped wiring substrate having interlayer insulation layers and a wiring layer that are alternately stacked. A cavity is defined in a central portion of the wiring substrate. A first insulation layer is arranged in the cavity so that a frame-shaped clearance exists between an outer side surface of the first insulation layer and an inner side surface of the wiring substrate as viewed from above. The cavity is filled with a second insulation layer. A contact terminal projecting from a lower surface of the first insulation layer is electrically connected to the wiring layer by a conductive wire. Elasticity of the second insulation layer is smaller than elasticity of each interlayer insulation layer.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: October 4, 2016
    Assignee: Shinko Electric Industries Co., LTD.
    Inventors: Michio Horiuchi, Ryo Fukasawa, Yuichi Matsuda, Yasue Tokutake
  • Patent number: 9442164
    Abstract: Detecting circuits are connected in parallel to respective on/off mechanical contacts or on/off semiconductor devices of a motor contactor and/or a brake contactor of a driving circuit supplying driving electric power from a three-phase alternating-current power supply circuit to a three-phase alternating-current electric motor and a brake through the motor contactor and the brake contactor, respectively. The detecting circuits output pulse signals synchronized with the alternating current from the alternating-current power supply circuit. A signal processing circuit processes the pulse signals from the detecting circuits and detects a normal or abnormal condition of each on/off mechanical contact or on/off semiconductor device of the motor contactor and/or the brake contactor.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 13, 2016
    Assignee: KITO CORPORATION
    Inventor: Yasuhiko Oyamada
  • Patent number: 9234916
    Abstract: A connector system comprising a status monitoring cable system comprising a first cable connector adapted to be connected to a generator connector, a second cable connector adapted to be connected to a UPS connector, a third cable connector adapted to be connected to the modem connector, a jumper, first and second power conductors connected between the first cable connector and the second cable connector, and a sensor module comprising a current detect module and a connector detect module. The current detect module transmits a GEN_ON signal to the modem when a current is present in at least one of the first and second power conductors. The connector detect module transmits a GEN_PRESENT signal to the modem when a current flows through the first cable connector, the generator connector, the jumper, the generator connector, and the first cable connector.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 12, 2016
    Assignee: Alpha Technologies Inc.
    Inventors: Tobias M. Peck, Jonathan D. Carpenter, Donald L. Thompson, Mike L. Foster