Abstract: A display device includes: a first substrate; a second substrate; first signal lines on the first substrate; second signal lines on the second substrate; first lateral wires on a lateral side of a first edge of the first substrate, and connected to end portions of the first signal lines; and second lateral wires on a lateral side of a second edge of the second substrate, and connected to end portions of the second signal lines. The first and second lateral wires are located in at least one first region and at least one second region, the at least one first region and the at least one second region being spaced from each other on the lateral sides of the first substrate and the second substrate. The at least one first region includes the first lateral wires, and the at least one second region includes the second lateral wires.

Abstract: Methods, systems, and devices are contemplated for assembling a genome from duplicate segments of the genome. Sequences with a first level of common neighboring base pairs are identified and organized into first level groups. Groups are then identified from the first level groups that have a second level of common neighboring base pairs and organized into a number of second level groups. A third level of groups can further be organized in some embodiments. Typically the second level groups are assembled into spans having contiguous base pair sequences, which are then assembled into the broader genome sequence. The inventive subject matter is preferably used for whole genome sequencing.

Abstract: A display device includes: a substrate including an opening and a display area surrounding the opening; a plurality of display elements in the display area and including a first display element and a second display element spaced apart from each other about the opening; an input sensing layer on the plurality of display elements and including two first sensing electrodes spaced apart from each other around the opening and two second sensing electrodes spaced apart from each other around the opening; and a plurality of segments between the opening and the display area, wherein the plurality of segments comprise: a first segment electrically connected to one of the two first sensing electrodes through a first line; and a second segment electrically connected to the first segment through a second line.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: A first conductive pattern and a third conductive pattern are joined to each other in a junction plane, and a second conductive pattern and a fourth conductive pattern are joined to each other in the junction plane, and an insulation layer is arranged at least in one of spaces between the first conductive pattern and the second conductive pattern and between the third conductive pattern and the fourth conductive pattern.

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

Abstract: A semiconductor structure includes a first redistribution structure, wherein the first redistribution structure includes first conductive pattern. The semiconductor structure further includes a die over the first redistribution structure. The semiconductor structure further includes a molding over the first redistribution structure, wherein the molding surrounds the die, and the molding has a first dielectric constant. The semiconductor structure further includes a dielectric member extending through the molding, wherein the dielectric member has a second dielectric constant different from the first dielectric constant. The semiconductor structure further includes a second redistribution structure over the die, the dielectric member and the molding, wherein the second redistribution layer includes an antenna over the dielectric member, and the antenna is electrically connected to the die.

Abstract: The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as memory data management of a NN/DNN. Using vector quantization of neuron weight values, the processing of data by neurons can be optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, one or more contiguous segments of weight values can be converted into one or more vectors of arbitrary length and each of the one or more vectors can be assigned an index. The generated indexes can be stored in an exemplary vector quantization lookup table and retrieved by exemplary fast weight lookup hardware at run time on the fly as part of an exemplary data processing function of the NN as part of an inline de-quantization operation to obtain needed one or more neuron weight values.

Abstract: The present disclosure provides a light emitting device and a method for manufacturing the same, and a display device, and relates to the technical field of display. The light emitting device includes: a pixel define layer; a plurality of sub-pixels, comprising a first sub-pixel and a second sub-pixel adjacent to and spaced apart from the first sub-pixel by the pixel define layer, wherein each of the plurality of sub-pixels comprises a functional layer; and a blocking member disposed on the pixel define layer.

Abstract: A display substrate, a preparation method thereof and a display apparatus. The display substrate comprises a substrate, multiple pixel units arranged on the substrate and a color filter layer arranged on the pixel unit, wherein the color filter layer comprises color optical filters of different colors and a touch control structure layer arranged between the color optical filters of different colors; the touch control structure layer comprises a touch control connection electrode, a first coating protective layer covering the touch control connection electrode and a touch control electrode arranged on the first coating protective layer, the touch control electrodes comprise a first touch control electrode and a second touch control electrode, and at least one of the first touch control electrode and the second touch control electrode is connected with the touch control connection electrode through a via hole penetrating through the first coating protective layer.

Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.

Abstract: A semiconductor package includes a redistribution structure, a first die, a second die and a buffer layer. The second die is disposed between the first die and the redistribution structure, and the second die is electrically connected to the first die and bonded to the redistribution structure. The buffer layer is disposed on a first sidewall of the second die, wherein a second sidewall of the buffer layer is substantially flush with a third sidewall of the first die.

Abstract: A system for estimating a dose from a proton therapy plan includes a memory that stores machine instructions and a processor coupled to the memory that executes the machine instructions to subdivide a representation of a volume of interest in a patient anatomy traversed by a planned proton field into a plurality of voxels. User input received by a GUI can be used to define the representation. The processor further executes the machine instructions to determine the distance from the source of the planned proton beam to one of the voxels. The processor also executes the machine instructions to compute the discrete contribution at the voxel to an estimated dose received by the volume of interest from the planned proton beam based on the distance between the source and the volume of interest.

Abstract: Provided is a display panel, including: a substrate comprising: a display region, a peripheral region and a pad region; a first dam; a planarization layer disposed within the first dam, wherein a first groove is defined between the first dam and the planarization layer, and wherein an edge of a first side of the planarization layer comprises a first segment boundary and a second segment boundary that are connected; a packaging layer covering the planarization layer; and a touch layer disposed on the packaging layer, wherein the touch layer comprises a touch signal line and a touch electrode pattern, the a touch electrode pattern being electrically connected to a pad in the pad region by the touch signal line which travels through the first segment boundary; wherein the packaging layer comprises an organic layer, an edge of the organic layer being disposed in the first groove.

Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Abstract: A semiconductor device has an electronic component assembly, and a plurality of discrete antenna modules disposed over the electronic component assembly. Each discrete antenna module is capable of providing RF communication for the electronic component assembly. RF communication can be enabled for a first one of the discrete antenna modules, while RF communication is disabled for a second one of the discrete antenna modules. Alternatively, RF communication is enabled for the second one of the discrete antenna modules, while RF communication is disabled for the first one of the discrete antenna modules. A bump is formed over the discrete antenna modules. An encapsulant is deposited around the discrete antenna modules. A shielding layer is formed over the electronic components assembly. A stud or core ball can be formed internal to a bump connecting the discrete antenna modules to the electronic component assembly.

Abstract: A package substrate may include a plurality of stacked insulation layers, a plurality of RDLs and a pair of impedance patterns. The RDLs may be arranged between the insulation layers. The impedance patterns may be arranged on an upper surface of at least one of the insulation layers. The impedance patterns may have an insulation length corresponding to a summed length of thicknesses of at least two insulation layers among the plurality of the insulation layers. Thus, a dummy conductive pattern may not be arranged between the impedance patterns and the RDL so that only the insulation layer may exist between the impedance patterns and the RDL. As a result, the insulation length of the impedance patterns may correspond to the summed length of the thicknesses of the at least two insulation layers.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.