Patents Examined by L. Donoghue
  • Patent number: 5537640
    Abstract: An asynchronous computer bus and method to maintain consistency of data contained in a cache and a memory which are each coupled to the bus. The bus comprises a cache hit indication means, a write access indication means, and a modified data indication means. A means is provided for invalidating a first portion of the cache, the invalidation means being operative upon activation of the cache hit indication means. Further, the bus comprises a modified data indication means and the write access indication means. A write-back means is provided for writing back the first portion of the cache data to the memory, the write back means being operative upon the first portion of the cache being invalidated by the invalidation means. Lastly, the bus comprises a shared data indication means which is operative on the cache hit indication means and upon failure of activation of the write access determination means.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: July 16, 1996
    Assignee: Intel Corporation
    Inventors: Stephen S. Pawlowski, Peter D. MacWilliams, David M. Cowan, Howard S. David
  • Patent number: 5504928
    Abstract: A method and apparatus for supporting multiple command sets in a single rendering adapter. A device driver operating in tandem with a rendering adapter and its associated microcode interprets disparate command sets without separate control/interpretation sections being maintained in the rendering adapter. Rendering adapter microcode in the adapter for supporting a first command set is extending to support commands in a second command set not capable of being mapped in the first command set. The device driver receives the disparate data stream command sets generated by application programs and destined for the rendering adapter. If a first command set command is received by the device driver, it is passed on to the rendering adapter substantially unmodified. If a second command set command is received by the device driver, an attempt is made to map the command into a first command set command, and then transfer this mapped command to the rendering adapter.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: April 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: John A. Cook, Linas L. Vepstas
  • Patent number: 5497499
    Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: March 5, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Sanjiv Garg, Kevin R. Iadonato, Le T. Nguyen, Johannes Wang
  • Patent number: 5410727
    Abstract: A two-dimensional input/output system for a massively parallel SIMD computer system providing an interface for the two-way transfer of data between a host computer and the SIMD computer. A plurality of buffers equal in number, and distributed with the individual processing elements of the SIMD computer are used to provide a temporary storage area which allows data in different formats to be mapped in a format suitable for transfer to the host computer or for transfer to the SIMD processing elements. The temporary storage is controlled in such a way as to transfer entire blocks of data in a single SIMD system clock cycle thereby achieving an input/output data rate of N bits/cycle for a SIMD computer consisting of N processors. The system is capable of handling irregular as well as regular data structures. The system also emphasizes a distributed approach in having the input/output system divided into N pieces and distributed to each processor to reduce the wiring complexity while maintaining the I/O rate.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: April 25, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert S. Jaffe, Hungwen Li, Margaret M. L. Kienzle, Ming-Cheng Sheng