Patents Examined by Lam T. Mai
  • Patent number: 10333204
    Abstract: An antenna component is disclosed. In an embodiment the antenna component including a first, second and third electrical conductors and a magnetic core integrally embodied having different section, wherein the first, second and third electrical conductors are located at different sections of the magnetic core.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 25, 2019
    Assignee: EPCOS AG
    Inventors: Felipe Jerez, Anneliese Drespling, Elmar Walter, Stephan Buehlmaier, Joern Schliewe
  • Patent number: 10333549
    Abstract: A system for encoding and decoding data-tokens. In some examples, the system may be configured to encode and decode integers. In other cases, the system may be configured to encode and decode symbols or bytes of data.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 25, 2019
    Assignee: iDensify LLC
    Inventors: Dan E. Tamir, Dan Bruck
  • Patent number: 10333214
    Abstract: It is an object of the present invention to provide compact and wideband array antennas based on multilayer substrate technologies which can be applied in lightweight radars. An antenna radiating element disposed in a multilayer substrate comprises a signal via; a plurality of ground vias surrounding the signal via; a radiation pad connected to one end of the signal via; a feed pad connected to another end of the signal vias; and an artificial medium disposed between the signal via and the ground vias; wherein the multilayer substrate comprises a plurality of conductor layers isolated by a dielectric material.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 25, 2019
    Assignee: NEC CORPORATION
    Inventor: Taras Kushta
  • Patent number: 10333539
    Abstract: A calibration method includes the following: providing a first charge quantity to a first input terminal of a comparator; providing a second charge quantity to a second input terminal of the comparator by one of multiple switch capacitor groups, and providing a compensation charge quantity to the second input terminal of the comparator by at least another one of the switch capacitor groups; comparing a voltage value received by the first input terminal and a voltage value received by the second input terminal, and outputting a voltage comparison result to a controller; and if the controller determines the charge quantity provided to the second input terminal approximates to the charge quantity provided to the first input terminal based on the voltage comparison result, recording a calibration charge quantity in a lookup table stored by the controller. An analog-to-digital converter and a calibration apparatus are also provided.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 25, 2019
    Assignee: ITE Tech. Inc.
    Inventor: Jun-Hong Hsu
  • Patent number: 10333540
    Abstract: An oscilloscope comprises a first channel that includes a first channel physical input adapted to receive a first input signal, and a first channel digitizer connectable to the first channel physical input. The oscilloscope comprises a second channel that includes a second channel physical input adapted to receive a second input signal, and a second channel digitizer connected to the second channel physical input. The oscilloscope comprises a switch to change the first channel digitizer from connecting to the first channel physical input, to connecting to the second channel physical input. The oscilloscope includes a combiner to combine an output of the first channel digitizer and an output of the second channel digitizer, when a high bandwidth mode is activated, to generate an output that has a bandwidth of frequency content that exceeds a bandwidth of the first digitizer and exceeds a bandwidth of the second channel digitizer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 25, 2019
    Assignee: Teledyne LeCroy, Inc.
    Inventors: Peter J. Pupalaikis, David C. Graef
  • Patent number: 10326469
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for segmenting a digital input signal for digital-to-analog conversion. For example, certain aspects provide a segmentation circuit for generating digital signal segments for a digital-to-analog converter. The segmentation circuit generally includes a modulo function logic circuit configured to generate a modulo output signal based on a digital input signal and a divisor input signal and a modulo range extension logic circuit configured to selectively direct the modulo output signal or the divisor input signal to an output of the segmentation circuit. In certain aspects, the output of the segmentation circuit may be used by the digital-to-analog converter to generate an analog signal based on the digital input signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: William Cope
  • Patent number: 10325010
    Abstract: Collating text strings having Unicode encoding includes receiving two text strings S=s1s2 . . . s and T=t1t2 . . . tm. When the two text strings are not identical, there is a smallest positive integer p for which the two text strings differ. The process looks up the characters sp and tp in a predefined lookup table. If either of these characters is missing from the lookup table, the collation of the text strings is determined using the standard Unicode comparison of the text strings spsp+1 . . . sn and tptp+1 . . . tm. Otherwise, the lookup table assigns weights vp and wp for the characters sp and tp. When vp?wp, these weights define the collation order of the strings S and T. When vp=wp, the collation of S and T is determined recursively using the suffix strings sp+1 . . . sn and tp+1 . . . tm.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 18, 2019
    Assignee: Tableau Software, Inc.
    Inventors: Thomas Neumann, Viktor Leis, Alfons Kemper
  • Patent number: 10320410
    Abstract: A circuit device includes a code data generation circuit that generates code data which changes with time, and a successive approximation type A/D conversion circuit that performs code shift based on the code data and performs A/D conversion of an input signal. The code data generation circuit generates error data of which a frequency characteristic has a shaping characteristic and converts the error data into the code data.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 11, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Haneda, Atsushi Tanaka
  • Patent number: 10312927
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Seyed Arash Mirhaj, Elias Dagher, Yongjian Tang, Dinesh Alladi, Masoud Ensafdaran, Lei Sun, Anand Meruva, Yuhua Guo, Balasubramanian Sivakumar
  • Patent number: 10312928
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 4, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 10312584
    Abstract: A dual antenna device comprises a substrate, a first antenna, a second antenna and an isolation element. The substrate comprises an installation surface, the first antenna and the second antenna protrude from the installation surface and respectively couple to the installation surface by the first grounding edge and the second grounding edge. The isolation element comprises a first isolation portion protruding from the installation surface and coupling to the installation surface by a bottom side of the first isolation portion so that the first antenna and the second antenna respectively locate at both sides of the isolation element. The first antenna and the isolation element form a first interval in the extension direction of the first grounding edge. The second antenna and the isolation element form a second interval in the extension direction of the second grounding edge. The design of the isolation element improves the isolation magnitude.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 4, 2019
    Assignee: LYNWAVE TECHNOLOGY LTD.
    Inventor: Shih-Chieh Chao
  • Patent number: 10312932
    Abstract: The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: June 4, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yohei Nakamura, Taizo Yamawaki
  • Patent number: 10305507
    Abstract: A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jerry Lee Doorenbos, Keith Eric Sanborn, Mina Raymond Naguib Nashed, Srikanth Vellore Avadhanam Ramamurthy, Dwight David Griffin
  • Patent number: 10303125
    Abstract: A time-to-digital converter includes first and second oscillation circuits, first and second sampling circuits, and a processing circuit. The first and second oscillation circuits start an oscillation operation in accordance with first and second signals and output first and second clock signals, respectively. The first and second sampling circuits perform sampling of the first and second clock signals by a first reference clock signal and output first and second output signals, respectively. The processing circuit obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first and second output signals of the first and second sampling circuits, and obtains a digital value corresponding to a time difference of a transition timing between the first and second signals.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 28, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Hideo Haneda
  • Patent number: 10298944
    Abstract: A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 21, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Kuan-Chou Lee, Kai-Wen Cheng, Tai-Lai Tung
  • Patent number: 10298253
    Abstract: Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: May 21, 2019
    Assignee: KOPIN CORPORATION
    Inventors: Dashen Fan, Joseph Yong Kwon
  • Patent number: 10298254
    Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 21, 2019
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY CHINA
    Inventors: Hua Fan, Jingxuan Yang, Quanyuan Feng, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari, Franco Maloberti, Jingtao Li, Huaying Su
  • Patent number: 10298256
    Abstract: An analog-to-digital conversion system includes two quantizers having a least significant bit arranged in a parallel pair. An input circuit coupled to the quantizers provides an analog input signal to the quantizers. A dither generator coupled to the quantizers provides an analog differential dither signal for perturbing quantization of the analog input signal. A combiner coupled to the quantizers adds respective outputs of the quantizers to obtain a linearized digital representation of the analog input signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Raytheon Company
    Inventors: Ian S. Robinson, James Toplicar, John G. Heston
  • Patent number: 10297920
    Abstract: A transmitter of a feed network includes first and second branches and an integrated branch line coupler that couples the first and second branches. The integrated branch line coupler includes first and second waveguide reject filters in the first and second branches respectively. The first and second waveguide reject filters include one or more single-sided stubs protruding outwardly from outer faces of the first and second waveguide reject filters. The integrated branch line coupler further includes one or more couplers that are coupled between inner faces of the first and second waveguide reject filters. The transmitter includes a core waveguide that is coupled to the first and second branches. The transmitter receives a linearly polarized signal from an input port of the first or second branches and generates a circularly polarized signal in the core waveguide.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: May 21, 2019
    Assignee: Lockheed Martin Corporation
    Inventor: Jason Stewart Wrigley
  • Patent number: 10297895
    Abstract: Aspects of the subject disclosure may include, for example, a system for generating first electromagnetic waves and directing instances of the first electromagnetic waves to an interface of a transmission medium to induce propagation of second electromagnetic waves having a dominant non-fundamental wave mode. Other embodiments are disclosed.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 21, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Paul Shala Henry, Robert Bennett, Farhad Barzegar, Irwin Gerszberg, Donald J. Barnickel, Thomas M. Willis, III