Patents Examined by Lam T. Mai
  • Patent number: 10784882
    Abstract: An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 22, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Man-Pio Lam
  • Patent number: 10784890
    Abstract: A signal processor and a method for processing an input signal are presented. The signal processor is adapted to clip an oversampled input signal without introducing noise in the frequency band of interest. For instance, the signal processor may be used for clipping an acoustic signal. The signal processor includes a summer coupled to a limiter and to a feedback circuit. The summer is adapted to sum the input signal with at least one feedback signal to provide an adjusted signal. The limiter is adapted to compare the adjusted signal with a first threshold value and a second threshold value to provide a limited signal. The feedback circuit is adapted to calculate a difference between the limited signal and the adjusted signal, and to generate at least one feedback signal based on the difference.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 22, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Ashley Hughes, Wessel Harm Lubberhuizen
  • Patent number: 10778246
    Abstract: A computer-implemented method according to one embodiment includes dividing data into a plurality of partitions, creating a plurality of groups of different data types within each of the plurality of partitions, independently compressing, within each of the plurality of partitions, each of the plurality of groups of different data types to create a plurality of independently compressed partitions, and validating each of the plurality of independently compressed partitions to create a plurality of validated independently compressed partitions.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: M Corneliu Constantinescu, Gero Friedrich Wolf Schmidt, Wayne A. Sawdon
  • Patent number: 10778241
    Abstract: The present disclosure may be embodied as an optical encoder system comprising a first optical sensor, a second optical sensor, a first up-down counter, a second up-down counter, and an I/O expander. The optical encoder system may further include a buffer. The present disclosure may also be embodied as an optical encoder system comprising an optical encoder, and a monostable multivibrator. The present disclosure may also be embodied as a method for encoding optical data comprising generating a first optical sensor signal and a second optical sensor signal, converting the first optical sensor signal and second optical sensor signal into four first counter signals, generating a borrow output signal and a carry output signal, converting the borrow output signal and the carry output signal into four second counter signals, and converting the first counter signals and second counter signals into a serial data signal and a serial clock signal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 15, 2020
    Assignee: Buffalo Automation Group Inc.
    Inventor: Trevor R. McDonough
  • Patent number: 10771087
    Abstract: In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 8, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jochen O. Schrattenecker, Peter Bogner, Andrea Cristofoli, Michael Kropfitsch
  • Patent number: 10770799
    Abstract: Aspects of the subject disclosure may include, a device with a polyrod antenna having a core, where the core has a first region with a first dielectric constant and a second region with a second dielectric constant, and where the second dielectric constant is higher than the first dielectric constant. The device can include a waveguide coupled with the core, where the waveguide is configured to confine an electromagnetic wave at least in part within the core in the first region. Other embodiments are disclosed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 8, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Shikik Johnson, David M. Britz, Irwin Gerszberg
  • Patent number: 10771075
    Abstract: A converter circuit is used to selectively convert an analog input voltage into a digital output signal or a digital input signal into an analog output voltage as a function of a mode signal. The converter circuit includes a control circuit configured to generate a start-of-conversion signal. A ramp generator is configured to, when the mode signal indicates an analog-to-digital conversion, generate a timer stop signal after a time interval that is determined as a function of the value of the analog input voltage, thereby implementing an analog-to-time conversion. When the mode signal indicates a digital-to-analog conversion, ramp generator is configured to vary the ramp signal until a ramp stop signal is set and, in response to the ramp stop signal, determine the analog output voltage as a function of the ramp signal, thereby implementing a time-to-analog conversion.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Manuela La Rosa, Giovanni Sicurella
  • Patent number: 10771084
    Abstract: A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 8, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Kimmo Koli
  • Patent number: 10763888
    Abstract: A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Chenming Zhang, Lucien Johannes Breems, Muhammed Bolatkale
  • Patent number: 10763882
    Abstract: A switch interface adapter allowing a simple open/close switch to be adapted to a digital and analog diagnostic switch interface includes: at least one coil having a first terminal and a second terminal, wherein the switch is electrically connected to the first terminal or the second terminal, and the at least one coil is activated or deactivated via the switch; a first contact switch comprising a digital line, wherein the at least one coil controls opening and closing of the first contact switch to break and complete the digital line respectively, the digital line is electrically connected to the ECU, and a digital signal is generated from the digital line as a digital input for the ECU; a second contact switch comprising an analog line, wherein the at least one coil controls opening and closing of the second contact switch to break and complete the analog line respectively, the analog line is electrically connected to the ECU, an analog signal is generated from the analog line as an analog input for the ECU
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 1, 2020
    Assignee: VOLVO TRUCK CORPORATION
    Inventor: Jason Stone
  • Patent number: 10763874
    Abstract: A signal processing system includes an adjustable filter, a signal difference calculating unit, a determining unit and a selecting unit. The adjustable filter is configured to receive a digital signal outputted from an analog-to-digital converter, and filter the digital signal to generate a filtered signal. The signal difference calculating unit is configured to calculate and output a signal difference value between the digital signal and the filtered signal. The determining unit is configured to compare the signal difference value with a predetermined threshold value, to generate a comparison result, and generate a selection signal and a bandwidth adjustment signal according to the comparison result. The selecting unit is configured to receive the digital signal and the filtered signal, and output one of the digital signal and the filtered signal according to the selection signal. The bandwidth of the adjustable filter can be adjusted according to the bandwidth adjustment signal.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Feng Shih
  • Patent number: 10763876
    Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 10749542
    Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 18, 2020
    Assignee: Luxtera LLC.
    Inventor: Oleksiy Zabroda
  • Patent number: 10749545
    Abstract: A data storage system performs partial compression and decompression of a set of memory items. The memory items each include a data block and a tag with a prefix making up at least part of the tag. The memory items are ordered based on the prefixes. A code word is created containing compressed information representing values of the prefixes for the set of memory items. The code word and block data for each of the memory items are stored in a memory. The code word is decompressed to recover the prefixes.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
  • Patent number: 10735014
    Abstract: An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Jie Pu, Gang-yi Hu, Dong-Bing Fu, Xi Chen, Xing-Fa Huang, Yu-Xin Wang, Guang-Bing Chen, Ru-Zhang Li
  • Patent number: 10735010
    Abstract: In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 4, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Hananel Faig, David Rohlin
  • Patent number: 10732577
    Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 4, 2020
    Assignee: NXP B.V.
    Inventors: Hao Fan, Michiel Pertijs, Berry Anthony Johannus Buter
  • Patent number: 10735016
    Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 4, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kunihiko Nakamura, Tomohiro Nezuka
  • Patent number: 10727861
    Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 28, 2020
    Assignee: MaxLinear, Inc.
    Inventors: Chandrajit Debnath, Abhishek Ghosh, Rishi Mathur, Anand Mohan Pappu
  • Patent number: 10720939
    Abstract: Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 21, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Yuichi Miyahara