Abstract: Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: A radar apparatus includes a transmission-reception antenna unit including a plurality of transmission antennas and a plurality of reception antennas along a predetermined array direction, which form a virtual array in which a plurality of virtual reception antennas are arranged along the array direction. Based on virtual reception signals received by the virtual reception antennas, the radar apparatus detects an object that reflects transmission signals, calculates a transmission phase difference between the transmission antennas of the transmission signals transmitted by the transmission antennas, and calculates a reception phase difference between the reception antennas of reception signals received by the reception antennas.

Abstract: Embodiments of the present disclosure include techniques for compressing data using a tree encoded bit mask that may result in higher compression ratios. In one embodiment, an input vector having a plurality of values is received by a first plurality of switch circuits. Selection of the input values is controlled by sets of bits from the bit mask. The sets of bits specify locations of portions of the input vector where particular value of interest reside. The switch circuits output multiple values of the input vector, which include the particular value of interest. A second stage of switch circuits is controlled by logic circuit that detects values on the outputs of the first stage of switch circuits and outputs the values of interest. In some embodiments, the values of interest may be non-zero values of a sparse input vector, and the switch circuits may be multiplexers.

Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

Abstract: The disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-generation (4G) communication system, such as long term evolution (LTE). A radiating element of an antenna is provided. The radiating element includes a vibrator radiating circuit board, wherein vibrator radiating arms arranged in pairs are printed on the vibrator radiating circuit board, a width of the vibrator radiating arms is less than one-half of a wavelength, a vibrator balun circuit board, configured to support the vibrator radiating circuit board, wherein a vibrator balun is printed on the vibrator balun circuit board, a height of the vibrator balun is at least less than one-fifth of the wavelength, the vibrator balun comprises at least one first slot.

Abstract: A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

Abstract: A hardware-programmable digital signal path component for processing events from sensor mixed signal devices. A system includes a mixed signal component and a reconfigurable signal path component. The mixed signal component includes a group of sensor devices and generates one or more events from among the group of sensor devices. The signal path component receives the event(s), and includes a control unit component and a digital signal processor (DSP) component. The control unit component includes a programmable function enable mechanism, and distributes the received event(s) in combination with one or more functions among a set of predefined functions enabled by the programmable function enable mechanism. The DSP component is configured to perform one or more operations associated with the distributed event(s) in accordance with the enabled function(s).

Abstract: The A/D converter includes a D/A conversion circuit configured to perform a D/A conversion on a DAC input digital value to output a DAC output signal, a difference output circuit for outputting difference signals based on a difference between the input signal and the DAC output signal, an A/D conversion circuit for performing an A/D conversion on the difference signals to output an ADC output digital value, and a control circuit for outputting the DAC input digital value based on the ADC output digital value. The control circuit outputs a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value, and obtains ADC result data based on a first ADC output digital value obtained in accordance with the first DAC input digital value, a second ADC output digital value obtained in accordance with the second DAC input digital value, and the DAC input digital value.

Abstract: An analog-to-digital converter is provided. The analog-to-digital converter includes: a sample/hold circuit; a digital-to-analog converter; a plurality of comparison circuits; a control logic; and a digital register, wherein the plurality of comparison circuits include: a first comparison circuit configured to output a first comparison result signal in a first operation period; a second comparison circuit configured to, in a second operation period, calibrate an offset of a second comparison result signal based on a reference signal corresponding to the first comparison result signal among a plurality of reference signals and output the calibrated second comparison result signal; and a third comparison circuit configured to, in a third operation period, calibrate an offset of a third comparison result signal based on a reference signal corresponding to the calibrated second comparison result signal and output the calibrated third comparison result signal.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Abstract: An electronic device includes a bracket including a first structure at least partially having non-conductivity, a second structure disposed on a first surface of the first structure and at least partially having conductivity, and an antenna pattern electrically connected with the second structure and disposed on a second surface of the first structure, and a printed circuit board including a grounding part and a feeding part. The grounding part is electrically connected with the second structure, and the feeding part is electrically connected with a portion of the antenna pattern.

Abstract: Techniques for facilitating analog-to-digital converter calibrations are provided. In one example, a method includes, for each of a plurality of time instances, generating a first ramp signal started at the time instance relative to a respective start of a first counter signal and generating a respective comparator output signal based on the first ramp signal and a first threshold signal. The method further includes capturing a respective first value of the first ramp signal in response to a transition of the respective comparator output signal. The method further includes determining a respective second counter value of a second counter signal based on the respective first value. The method further includes determining a scaling factor based on the second counter values and the time instances. Each of the first values is associated with the same counter value of the first counter signal. Related devices and systems are also provided.