Patents Examined by Lam T. Mai
  • Patent number: 11664814
    Abstract: Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 30, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Gerard Mora Puchalt, Italo Carlos Medina Sánchez Castro, Jesús Bonache Martinez
  • Patent number: 11664576
    Abstract: The present invention concerns a vehicle antenna glazing antenna element. According to the present invention, the antenna element is placed on an outwardly oriented face of the glazing and the antenna is working at a frequency comprised between 750 MHZ and 28 GHZ. The antenna 5 element is connected to a co-axial cable.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 30, 2023
    Assignee: AGC GLASS EUROPE
    Inventor: Shimo Kenichiro
  • Patent number: 11658386
    Abstract: An antenna unit for glass according to the present invention is installed on the indoor side of a glass sheet, and transmits and receives electromagnetic waves at the indoor side through the glass sheet.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: May 23, 2023
    Assignees: AGC Inc., NTT DOCOMO, INC.
    Inventors: Tetsuya Hiramatsu, Ryuta Sonoda, Osamu Kagaya, Kentaro Oka, Akira Saito, Kensuke Miyachi, Akinobu Ueda, Yoshiyuki Kawano, Jun Andou, Taku Yamazaki
  • Patent number: 11658678
    Abstract: Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 23, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Preston S. Birdsong, Adam R. Spirer
  • Patent number: 11658672
    Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Ramon Sanchez, Kameran Azadet
  • Patent number: 11648400
    Abstract: The disclosure describes an implementation of a combinational thermometric-R2R that includes a thermometric DAC circuit to output the coarse output steps, an R2R circuit to control the fine output steps, and a resistor in series with the thermometric and R2R circuits. The techniques of this disclosure implement a fine resolution DAC, on the order of two nanoamps per bit, that operates at low current, yet maintains monotonicity throughout the DAC output range.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 16, 2023
    Assignee: MEDTRONIC, INC.
    Inventors: Krishna Pramod Madabhushi, Robert W. Hocken, Jr.
  • Patent number: 11652285
    Abstract: A cover for at least one antenna emitting and/or sensing electromagnetic radiation in at least one first frequency band includes at least one first surface facing the antenna and at least one second surface averted to the antenna, and at least one first carrier layer into which hat least one heating element is embedded, the heating element being connected to a terminal at least partly extending from the first surface and/or being at least partly located on the first surface.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 16, 2023
    Assignee: Motherson Innovations Company Limited
    Inventors: Garry Gordon Leslie Fimeri, Dean Caruso
  • Patent number: 11652494
    Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a discrete set of analog dither offset voltages, wherein at least two of the discrete set of analog dither offset voltages are different from each other, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein the waveform has a waveform duration, generate a timing alignment to align each waveform of the analog repetitive signal and the corresponding analog dither offset voltage over the waveform duration, combining, based on the timing alignment, each waveform and the corresponding analog dither offset voltage over the waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 16, 2023
    Assignees: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC, TEKTRONIX, INC.
    Inventors: Brandon Walter Buckley, Ryan Douglas Muir, Daniel G. Knierim
  • Patent number: 11641056
    Abstract: [Problems to be Solved] To provide a flight vehicle and a communication system which can relay communications between transmission and reception antennae that are located farther from each other by using antennae capable of receiving information transmitted from a transmission antenna located in a wider range than a range of a linear directed antenna can receive. [Solution] A flight vehicle 1 according to the present invention comprises one or more linear array antennae (antennae 4); and a controller 2 configured to be capable to execute: a process of receiving information by one or more of the antennae 4, a process of outwardly transmitting said information by one or more of the antennae 4. In the communication system C of the present invention, which includes said flight vehicle 1, the transmission antenna T1 and the reception antenna R1 differ from each other.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: May 2, 2023
    Assignee: WaveArrays, Inc.
    Inventor: Nobuyuki Kaya
  • Patent number: 11637559
    Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: April 25, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Patent number: 11637563
    Abstract: A decoding circuit and a chip are disclosed. The decoding circuit includes, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit. The charge/discharge unit is able to charge and discharge the capacitor, and a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value. The conversion unit is configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 25, 2023
    Assignee: SHANGHAI XINLONG SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Ruiping Li, Wei Chi, Bin Liu, Jianhu Wang
  • Patent number: 11636057
    Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: April 25, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Engin Ipek, Bohuslav Rychlik, George Patsilaras, Prajakt Kulkarni, Can Hankendi, Fahad Ali, Jeffrey Gemar, Matthew Severson
  • Patent number: 11637565
    Abstract: One example method includes file specific compression selection. Compression metrics are generated for a chunk of a file using a reference compressor. Compression metrics for other compressors are determined from the metrics of the reference compressor. A compressor is then selected to compress the file.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 25, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rômulo Teixeira De Abreu Pinho, Vinicius Michel Gottin, Joel Christner
  • Patent number: 11626886
    Abstract: Methods, systems, and devices for thermometer coding for driving non-binary signals are described. A set of drivers may be used to drive a signal line, with each of the drivers calibrated to have different individual drive strengths. To drive a signal line to successive voltages in accordance with a non-binary modulation scheme, additional individual drivers of the set may be used. The different drive strengths of the individual drivers of the set may scale in non-linear fashion, which may offset non-linearities associated with the individual drivers as additional individual drivers of the set are activated.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Dragos Dimitriu
  • Patent number: 11621722
    Abstract: The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 4, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Akira Shikata
  • Patent number: 11616512
    Abstract: A series-connected delta-sigma modulator (DSM) comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal, and to feed back the first quantized signal to the first loop filter, wherein the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal, and to feed back the second quantized signal to the second loop filter, wherein the second quantized signal comprises a quantization error smaller than a second predetermined value.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 28, 2023
    Assignee: National Cheng Kung University
    Inventor: Tai-Haur Kuo
  • Patent number: 11616509
    Abstract: A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Francesco Lombardo, Dmytro Cherniak, Luigi Grimaldi, Nicolo Guarducci
  • Patent number: 11611351
    Abstract: In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Maher Mahmoud Sarraj
  • Patent number: 11606099
    Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Veeramanikandan Raju, Anand Kumar G
  • Patent number: 11606102
    Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: March 14, 2023
    Assignee: NXP B.V.
    Inventors: Chenming Zhang, Marcello Ganzerli, Pierluigi Cenci, Lucien Johannes Breems