Patents Examined by Larry T Mackall
  • Patent number: 12197341
    Abstract: Aspects described herein relate to a method comprising: receiving a request to write data to a persistent storage device, the request comprising data; determining an affinity of the data; writing the request to a cache line of a cache; associating the cache line with the affinity of the data; and reporting the data as having been written to the persistent storage device.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: January 14, 2025
    Assignee: Daedalus Cloud LLC
    Inventors: Stuart John Inglis, Cameron Ray Simmonds, Dmitry Lapik, Chia-Chi Hsu, Daniel James Nicholas Stokes, Adam Gworn Kit Fleming
  • Patent number: 12197346
    Abstract: A controller assigns, for each namespace, one logical area of a logical address space as a first logical area including a last logical address of the namespace and assigns one or more of logical areas as second logical areas. The controller divides a memory region in which an address translation table is stored into buffer regions. For each second logical area, the controller assigns one buffer region for storing map segments corresponding to the second logical area, and manages a first pointer indicating a storage location of the buffer region assigned thereto. The controller also assigns one buffer region for map segments corresponding to the first logical areas of two or more namespaces, and manages second pointers respectively indicating storage locations in the one buffer region, in which the map segments corresponding to the first logical areas of the two or more namespaces are respectively stored.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventor: Mitsunori Tadokoro
  • Patent number: 12197783
    Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: January 14, 2025
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hua-Ling Cynthia Hsu, Fanglin Zhang
  • Patent number: 12189537
    Abstract: A memory system includes a first memory, a second memory, and a controller. The controller is configured to store address mapping information in the first memory, store, in the second memory, a mapping update data that is generated each time data writing to the first memory is performed, and upon an amount of mapping update data that have not been transmitted to the host reaching a threshold, transmit the address mapping information in the first memory and the mapping update data in the second memory to the host and cause the host to store updated address mapping information in a third memory in the host. The controller is configured to perform address mapping using the address mapping information in the first memory and the mapping update data in the second memory when connection with the host is lost.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: January 7, 2025
    Assignee: Kioxia Corporation
    Inventor: Fumio Hara
  • Patent number: 12175079
    Abstract: Provided herein may be a memory controller and a storage device including the same. The storage device may include a memory device including a plurality of memory cell arrays configured to store user data, a hardware accelerator configured to search for map data related to the user data, and a memory controller configured to control, in response to a first request received from a host, the memory device and the hardware accelerator to perform an operation corresponding to the first request, determine, when a second request is received from the host, whether the second request requires an operation of the hardware accelerator to transfer a dummy command to the hardware accelerator.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: December 24, 2024
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 12175082
    Abstract: A method and an apparatus for dynamically managing a shared memory pool are provided, to determine, based on different service scenarios, a shared memory pool mechanism applicable to a current service scenario, and then dynamically adjust a memory pool mechanism based on the determined result. The method for dynamically managing a shared memory pool includes: determining a first shared memory pool mechanism for the shared memory pool, where the first shared memory pool mechanism is a fixed memory pool mechanism or a dynamic memory pool mechanism; determining a second shared memory pool mechanism suitable for a second service scenario based on the second service scenario, where the second shared memory pool mechanism is a fixed memory pool mechanism or a dynamic memory pool mechanism; and when the second shared memory pool mechanism is different from the first shared memory pool mechanism, adjusting the first shared memory pool mechanism to the second shared memory pool mechanism.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: December 24, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Guofeng Zhu, Quancai Li, Jiansheng Tang
  • Patent number: 12169479
    Abstract: The present invention makes it possible to maintain availability and scale out file performance, while suppressing costs. A unified storage has a plurality of controllers and a storage apparatus (storage device unit), and each of the plurality of controllers is equipped with one or more main processors (CPU) and one or more channel adapters (FE-I/F). Each main processor causes a block storage control program to operate and thereby process data inputted to and outputted from the storage apparatus, each channel adapter has a processor (CPU) that performs transmission and reception to and from a main processor after receiving an access request, and the processors in the plurality of channel adapters cooperate to cause a distributed file system to operate, and distributively store data, written as a file, to the plurality of controllers.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: December 17, 2024
    Assignee: HITACHI VANTARA, LTD.
    Inventors: Yuto Kamo, Mitsuo Hayasaka, Norio Shimozono
  • Patent number: 12164779
    Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising responsive to receiving a memory access command, determining a portion of the memory device that is referenced by a logical address specified by the memory access command; determining an endurance factor associated with the portion; and modifying, based on a value derived from the endurance factor, a media management metric associated with the portion of the memory device.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: December 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Seungjune Jeon, Zhenlei Shen
  • Patent number: 12159050
    Abstract: Conversion to a virtual target may be performed for a source of a data store migration. A request that selects one of multiple data store conversion targets as a virtual target of data store migration from a source of the data store migration may be received. One or more conversion scripts for the data store migration may be generated based on an analysis of a possible conversion between the source of the data store migration and the virtual target of the data store migration using metadata obtained from the source of the data store migration that describes the source of the data store migration and a model corresponding to the virtual target of the data store migration. The conversion scripts may be stored for later execution.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 3, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Igor Bekelman, Mykyta Sokolov, Svitlana Malik, Mykhailo Silin, Irena Balin, Yuriy Yaroshenko, Vladyslav Tkachuk
  • Patent number: 12147710
    Abstract: The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks each including a plurality of pages. The controller is configured to sequentially write data from a first page of the plurality of pages when data is written on the plurality of pages. The controller records management information relating to the plurality of blocks in the first page of each of the plurality of blocks.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: November 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yu Nakanishi, Kazuhiro Hiwada
  • Patent number: 12141473
    Abstract: Methods, systems, and devices for performance tuning for a memory device are described. In some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. The indicator may instruct the memory system to suppress one or more portions of the command. For example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. Upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 12, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Liang Ge
  • Patent number: 12141480
    Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: November 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongik Jeon, Kyungbo Yang, Seokwon Ahn, Hyeonwu Kim
  • Patent number: 12124740
    Abstract: The present disclosure includes systems and methods for reducing rewrite overhead in a sequential access storage system. The method may comprise writing a data set to a sequential access medium using a magnetic head, wherein the data set comprises a plurality of encoded data blocks, classifying each of the plurality of encoded data blocks on the sequential access medium into one of at least three classes of write quality, and rewriting the encoded data blocks in a rewrite area of the sequential access medium based at least in part on the write quality class. In some embodiments, the at least three classes of write quality may comprise a hard rewrite class for which rewrites are necessary to prevent data loss, a soft rewrite class for which rewrites are desirable but not necessary, and a no rewrite class for which no rewrite is needed or desired.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: October 22, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ernest Stewart Gale, Roy Cideciyan, Simeon Furrer, Masayuki Iwanaga, Keisuke Tanaka
  • Patent number: 12118235
    Abstract: Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: October 15, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Paul Hanham, Julien Margetts, Matthew Stephens
  • Patent number: 12105594
    Abstract: Embodiments for processing fastcopy overwrite backup workloads (FCOW) as virtual synthetic backups, by detecting whether or not a backup workload comprises an FCOW workload in which a base file is fastcopied to a target file, wherein portions of the base file are overwritten through overwrites by new data in the target file by a deduplication backup process. For FCOW workloads, the process creates a file recipe by trapping seek offsets and write byte lengths for the overwrites, and writing extent information comprising offset differences to a recipe table of the file recipe, and the file recipe facilitates file processing optimizations including differencing, replication, and tiering.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products L.P.
    Inventors: Nitin Madan, Bhimsen Bhanjois, Kalyan C. Gunda
  • Patent number: 12105985
    Abstract: The invention is notably directed to a method of processing data in-memory. The method applies electrical signals to at least two input lines, which correspond to at least two rows. These two rows include at least one of the K rows and at least one of the L rows. This causes to obtain output signals in output of the M output lines, wherein the output signals depend on target values and operand values, in accordance with data stored across said at least two rows. Finally, the output signals are read out and a transformation operation is concurrently performed, in-memory, on the target values based on the operand values. This way transformed data are obtained by way of in-memory processing. The transformation may for instance be a cryptographic operation; the operand data may encode a cryptographic key. The invention is further directed to related apparatuses and systems, notably cryptographic service systems.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 1, 2024
    Assignee: International Business Machines Corporation
    Inventors: Iason Giannopoulos, Navaneeth Rameshan, Vara Sudananda Prasad Jonnalagadda, Abu Sebastian
  • Patent number: 12105955
    Abstract: Methods, systems, and devices for memory operations across banks with multiple column access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: October 1, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet V. Ayyapureddi
  • Patent number: 12099733
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The at least one processing device is configured to implement a source multi-path device between a source access device and a source logical storage device, to implement a target multi-path device between a target access device and a target logical storage device, and to initiate a data migration process to migrate data from the source logical storage device to the target logical storage device. The at least one processing device is further configured, in conjunction with the data migration process, to copy a set of paths of the source multi-path device to the target multi-path device, and to at least temporarily provide to the source access device identifying information of the source logical storage device in place of identifying information of the source multi-path device.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: September 24, 2024
    Assignee: Dell Products L.P.
    Inventors: Kurumurthy Gokam, Mohammad Salim Akhtar
  • Patent number: 12093567
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: performing a first write operation based on a first programming mode to sequentially write first data to a plurality of first chip enabled regions via a plurality of channels; after the first write operation is performed, performing a second write operation based on a second programming mode to sequentially write second data to the first chip enabled regions and at least one second chip enabled region via the channels. A total number of the first chip enabled regions is larger than a total number of the second chip enabled region.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: September 17, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Teng-Chun Hsu, Chang Han Hsieh
  • Patent number: 12093178
    Abstract: Database objects are retrieved from a database and parsed into normalized cached data objects. The database objects are stored in the normalized cached data objects in a cache store, and tenant data requests are serviced from the normalized cached data objects. The normalized cached data objects include references to shared objects in a shared object pool that can be shared across different rows of the normalized cached data objects and across different tenant cache systems.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: September 17, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Subrata Biswas