Patents Examined by Larry T Mackall
  • Patent number: 10847242
    Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 24, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Adolf Baumann, Mark Jung
  • Patent number: 10846093
    Abstract: In one embodiment, an apparatus includes: a value prediction storage including a plurality of entries each to store address information of an instruction, a value prediction for the instruction and a confidence value for the value prediction; and a control circuit coupled to the value prediction storage. In response to an instruction address of a first instruction, the control circuit is to access a first entry of the value prediction storage to obtain a first value prediction associated with the first instruction and control execution of a second instruction based at least in part on the first value prediction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Sumeet Bandishte, Jayesh Gaur, Sreenivas Subramoney, Hong Wang
  • Patent number: 10846023
    Abstract: When a real area is allocated to a write destination virtual area in a virtual volume, a storage device determines whether or not a size of compressed new data is larger than a size of the allocated real area. In a case where the determination result is true, the storage device determines whether or not there is one or more real areas having a size equal to or larger than the size of the compressed new data and including a garbage area that is a real area serving as garbage. In a case where the determination result is true, the storage device selects one or more real areas including the garbage area, allocates, instead of the allocated real area, the selected one or more real areas to the write destination virtual area, and manages the allocated real area as a garbage area.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: November 24, 2020
    Assignee: HITACHI, LTD.
    Inventors: Ai Satoyama, Tomohiro Kawaguchi, Yoshihiro Yoshii
  • Patent number: 10838661
    Abstract: A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Alex Bazarsky, Idan Alrod
  • Patent number: 10838646
    Abstract: A memory module or a storage device comprises a volatile memory subsystem, a non-volatile memory subsystem, and a controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The memory module or storage device further comprises a data selection circuit that pre-search data from the non-volatile memory with respect to one or more search criteria received from a computer system to pre-select data relevant to the one or more search criteria for loading into the volatile memory subsystem.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 17, 2020
    Assignee: NETLIST, INC.
    Inventor: Hyun Lee
  • Patent number: 10838865
    Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Leidel, Richard C Murphy
  • Patent number: 10838884
    Abstract: A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Apple Inc.
    Inventors: Thejasvi Magudilu Vijavaraj, Sukalpa Biswas, Lakshmi narasimha murthy Nukala, Gregory S. Mathews
  • Patent number: 10838635
    Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list. Another aspect includes, based on freeing of the last allocation on the first memory page, setting, by the processor, a first hidden flag in a first page table entry corresponding to the first memory page.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Griffith, Sreenivas Makineedi, Srinivasa Rao Muppala, Evan Zoss, Mathew Accapadi, Anil Kalavakolanu
  • Patent number: 10831410
    Abstract: A method for managing a storage system. The method includes one or more computer processors receiving a first set of data associated with a storage system. The method further includes determining whether to service the storage system based on utilizing one or more models associated with the storage system to analyze the first set of data. In response determining to service the storage system, the method further includes generating a set of notifications based, at least in part, on information from the one or more models associated with the storage system analyzing the first set of data. The method further includes initiating a pre-service activity associated the storage system based, at least in part, on information within the set of notifications.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Emmanuel Barajas Gonzalez, Shaun E. Harrington, Benjamin K. Rawlins, Jason E. Willerup
  • Patent number: 10825496
    Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard C Murphy
  • Patent number: 10824566
    Abstract: In a storage device according to the present invention, controllers each having a cache memory manage duplication of cache data. A storage device SD includes multiple controllers 1 each including a cache memory, and multiple storing units 21 used by the controllers and configured with logical volume 24 for being provided to a higher-level device 3. Each of the controllers, in a case where a paired destination controller forming a duplication pair is blocked, selects a new paired destination controller for each logical volume, forwards the cache data stored in the cache memory included in the own controller to the new paired destination controller, and stores the cache data in a cache memory included in the new paired destination controller to duplicate the cache data.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: November 3, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takashi Kaga, Tomohiro Nishimoto
  • Patent number: 10817198
    Abstract: The present disclosure is related to field of data backup in storage environment, and a method and system for dynamically controlling backup data on storage devices. A data allocating system may pool storage devices and backup data corresponding to client devices. Further performance parameters of storage devices may be evaluated for a pre-set time period based on which a rank is assigned to each of the plurality of storage devices based on performance parameters. Upon assigning the rank, the load characteristics and performance characteristics may be evaluated for each client device for the pre-set time period based on which a performance load index is determined for each client device. Finally, backup data of each client device may be dynamically allocated to each storage device by correlating rank and performance load index. The present disclosure reduces load on single storage device and increases efficiency by reducing delay in backing up data.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: October 27, 2020
    Assignee: Wipro Limited
    Inventors: Mohideen Abdul Kadar, Chandramohan Achar
  • Patent number: 10809937
    Abstract: Disclosed is a computer-implemented method to increase the speed of extent migration. The method comprises determining a plurality of extents to migrate. The extents are stored in a source tier and the source tier is one tier of a tiered storage system. The method also comprises forming a first queue, wherein the first queue contains the plurality of extents to be migrated. The method further includes selecting a first extent to copy to a target tier. The copying comprises dividing the extent into a plurality of strides, forming a second queue containing the strides, selecting and copying the first stride, and removing the first stride from the second queue. The method further comprises changing a mapping table to point to the target tier, removing the first extent from the first queue, and releasing the first area of the first tier.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hui Zhang, Bo Zou, Yongjie Gong
  • Patent number: 10809927
    Abstract: A virtual disk is instantiated as a representation of a storage volume. The virtual disk is configured with metadata corresponding to the storage volume. A storage stack is instantiated that is operable to provide an active I/O path to the storage volume. The storage stack is modified by adding an alternative I/O path to the virtual disk. The alternative I/O path includes a layout driver configured to manage a converted storage layout for the storage volume. The storage volume is encapsulated to the virtual disk. The active I/O path is closed and the alternative I/O path is enabled for I/O requests to the virtual disk. The storage layout of the storage device is converted without taking the storage volume offline.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karan Mehra, Vinod R. Shankar, Taylor Alan Hope
  • Patent number: 10809940
    Abstract: A first storage node configured to store data associated with a user is allocated. The data stored on the first storage node is mirrored at a second storage node. A resiliency mechanism is implemented at the first and second storage nodes. The resiliency mechanism is configured to restore data on at least one of the storage devices of the first and second storage nodes. In response to a loss of availability of either the first or second storage node and a loss of availability of one or more storage device on an available storage node, data on the unavailable storage devices of the available storage node is recovered using the resiliency mechanism of the available storage node.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 20, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karan Mehra, Justin Sing Tong Cheung, Vinod R. Shankar, Grigory Borisovich Lyakhovitskiy
  • Patent number: 10810125
    Abstract: A prefetch controller is configured to communicate with a prefetch cache in order to increase system performance. The prefetch controller includes an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller further includes a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller further includes a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller includes an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ahmed H. El-Mahdy, Hisham Emadeldin ElShishiny
  • Patent number: 10802962
    Abstract: A memory device and a control method for a non-volatile memory are provided. The non-volatile memory includes a target erasing region and an unselected region. The control method includes: erasing a target memory cell in the target erasing region. The unselected region is a region, excluding the target erasing region, in the non-volatile memory. The step of erasing the target memory cell includes an erasing operation, a verification operation, and an erasing loop after failing to pass the verification operation. The number of times of performing the erasing loop is an integer greater than or equal to 0. The control method further includes: refreshing a pre-defined portion in the unselected region, wherein a capacity of the pre-defined portion is determined by the number of times of performing the erasing loop.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 13, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chung-Meng Huang
  • Patent number: 10802752
    Abstract: A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiro Miomo, Prashob Ramachandran Nair, Hajime Yamazaki, Makoto Domon, Yasunori Nakamura
  • Patent number: 10802968
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Patent number: 10795587
    Abstract: It is determined whether the importance of an object storage node is equal to or larger than a predetermined importance and the reliability of the object storage node is equal to or larger than a predetermined reliability, the object storage node being a storage node set as an object among N storage nodes that are members of a storage cluster, N being an integer equal to or larger than 3. When the determination result is true, reintegration of the object storage node is performed. The importance of the object storage node depends on highness of availability when assuming that the object storage node has left the storage cluster. The reliability of the object storage node depends on the tendency of operation of the object storage node.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 6, 2020
    Assignee: HITACHI, LTD.
    Inventors: Akira Urakami, Takayuki Abe