Patents Examined by Lauren R Bell
  • Patent number: 9679974
    Abstract: According to one embodiment, a nitride semiconductor element includes: a stacked body; and a functional layer. The stacked body includes a first GaN layer, a first layer, and a second GaN layer. The first GaN layer includes a first protrusion. The first layer is provided on the first GaN layer and contains at least one of Si and Mg. The second GaN layer is provided on the first layer and includes a second protrusion. Length of bottom of the second protrusion is shorter than length of bottom of the first protrusion. A functional layer is provided on the stacked body and includes a nitride semiconductor.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9666796
    Abstract: A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 30, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Peng Liu, Yang Wu, Qun-Qing Li, Kai-Li Jiang, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 9653420
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 9627580
    Abstract: A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: April 18, 2017
    Assignee: Trustees of Boston University
    Inventors: Yitao Liao, Theodore D. Moustakas
  • Patent number: 9608118
    Abstract: An array substrate, a display device and a method of producing the array substrate are provided, and the array substrate includes a substrate and a thin film field effect transistor and a data line formed on the substrate, and the thin film field effect transistor includes a gate electrode, an active layer, a source electrode and a drain electrode, a gate insulating layer is formed between the gate electrode and the active layer, and the array substrate includes: a protection layer formed between the gate insulating layer and the data line and being in direct contact with the data line; and the protection layer is provided on the same layer with and has the same material with the active layer.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: March 28, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiangyang Xu, Lei Du, Sheng Wang
  • Patent number: 9590043
    Abstract: A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 7, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Lei Fang
  • Patent number: 9583689
    Abstract: An LED package includes a chip carrier, an adhesive layer, one high-voltage LED die, and an encapsulating member. The chip carrier defines a receiving space. The adhesive layer is disposed in the receiving space and has a thermal conductivity of larger than or equal to 1 W/mK. The high-voltage LED die is attached to the adhesive layer to be received in the reflective space and has a top surface formed with a trench. The trench of the high-voltage LED die is disposed at an optical center of the receiving space. The encapsulating member encapsulates the high-voltage LED die and includes a plurality of diffusers. The trench is embedded with the encapsulating member and has a width ranging from 1 ?m to 10 ?m and a depth of less than or equal to 50 ?m.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 28, 2017
    Assignees: Lite-On Opto Technology (Changzhou) Co., Ltd., Lite-On Technology Corp.
    Inventors: Yi-Fei Lee, Tsan-Yu Ho, Shih-Chang Hsu, Chen-Hsiu Lin
  • Patent number: 9570529
    Abstract: An organic light emitting diode (OLED) display including a display substrate; a sealing member facing the display substrate; a sealant between the display substrate and the sealing member, the sealant cohering the display substrate and the sealing member; a plurality of conductive wires on the display substrate and overlapping the sealant; and a heat blocking film between the conductive wire and the sealant, the heat blocking film including a plurality of sub-heat blocking films.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Zail Lhee
  • Patent number: 9548292
    Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 17, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Patent number: 9525076
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho Lee, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jin-seong Heo
  • Patent number: 9515150
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Junjie Xiong, Dongho Cha, Myung Jin Kang, Kihoon Do
  • Patent number: 9515241
    Abstract: A metallic frame of an LED structure includes two conductive frames spaced apart from each other with a gap and a plurality of extending arms respectively and integrally extended from the conductive frames. Each conductive frame includes a top surface, a bottom surface, and a lateral surface connecting the top and bottom surfaces. Each top surface comprises a sealed region and a mounting region surrounded by the sealed region, and the sealed and mounting regions of each conductive frame are defined by an insulating body. Each conductive frame has at least one slot concavely formed on the sealed region, and the lateral surface is formed with two openings and the slot is communicated with the two openings, such that the slot of each of the conductive frames is configured to separate at least one of the extending arms from the mounting region of the conductive frames.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 6, 2016
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventor: Chen-Hsiu Lin
  • Patent number: 9508929
    Abstract: A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 29, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Peng Liu, Yang Wu, Qun-Qing Li, Kai-Li Jiang, Jia-Ping Wang, Shou-Shan Fan
  • Patent number: 9496211
    Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
  • Patent number: 9455383
    Abstract: A molded package, comprising: a molded resin having a recess for accommodating a light emitting element; a ceramic substrate disposed in a bottom of the recess, the ceramic substrate having one surface exposed from the bottom of the recess and the other surface exposed from a rear surface of the molded resin; and a lead disposed at a lower part of the molded resin, the light emitting element being mounted on the one surface of the ceramic substrate, the lead being in contact with at least one side surface of the ceramic substrate to hold the ceramic substrate.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: September 27, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Kunihito Sugimoto, Keisuke Sejiki
  • Patent number: 9443773
    Abstract: Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 13, 2016
    Assignee: NXP B.V.
    Inventors: Tony Vanhoucke, Anco Heringa, Johannes Josephus Theodorus Martinus Donkers, Jan Willem Slotboom
  • Patent number: 9444033
    Abstract: Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: September 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonchul Cho, Ken Tokashiki
  • Patent number: 9425216
    Abstract: The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for the fringe field type flat panel displays and a method for manufacturing the same. The thin film transistor substrate having an oxide semiconductor layer can include a substrate including pixel region; a gate element formed on the substrate; a gate insulating layer covering the gate element; a channel layer on the gate insulating layer, a source area expanded form a first side of the channel layer, a drain area expanded from a second side of the channel layer, and a pixel electrode expanded from the drain area to the pixel region; an etch stopper formed on the channel layer; a data element formed on the etch stopper; and a common electrode formed on the passivation layer and within the pixel region.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 23, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hun Jang, Sul Lee
  • Patent number: 9397261
    Abstract: A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure under the transmissive substrate and including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer; a first electrode under the first conductive semiconductor layer; a reflective electrode layer under the second conductive semiconductor layer; a second electrode under the reflective electrode layer; a first connection electrode under the first electrode; a second connection electrode under the second electrode; and an insulating support member around the first electrode and the first connection electrode and around the second electrode and the second connection electrode and including a ceramic-based thermal diffusion agent.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 19, 2016
    Assignee: LG Innotek Co., Ltd.
    Inventors: Pil Geun Kang, Hee Seok Choi, Seok Beom Choi, Ju Won Lee, Deok Ki Hwang, Young Ju Han
  • Patent number: 9356012
    Abstract: An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee