Patents Examined by Lauren R Bell
  • Patent number: 9293452
    Abstract: An IC design that has an ESD transistor is disclosed. The IC includes a transistor, a ballast resistor, a routing structure and a coupling. The transistor includes a gate, a source and a drain. The ballast resistor is extending parallel to the gate of the transistor. The coupling connects the source of the drain of the transistor the ballast resistor. The routing structure connects the ballast resistor to the remaining of the circuitry. A method to design the IC is also disclosed. The ESD transistor provides means of protection against the ESD surges.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: March 22, 2016
    Assignee: Altera Corporation
    Inventors: Nor Razman Md Zin, Yanzhong Xu
  • Patent number: 9287209
    Abstract: Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 15, 2016
    Assignee: Broadcom Corporation
    Inventors: Agnes Neves Woo, Pascal Tran, Akira Ito, Guang-Jye Shiau, Chao-Yang Lu, Jung Wang
  • Patent number: 9263384
    Abstract: Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies AG
    Inventor: Frank Huebinger
  • Patent number: 9216557
    Abstract: A sealed structure which has high sealing capability and whose border can be slim is provided. The sealed structure includes a pair of substrates whose respective surfaces face each other with a space therebetween, and a glass layer which is in contact with the substrates, defines a space between the substrates, and has at least one corner portion and side portions in continuity with the corner portion. The width of the corner portion of the glass layer is smaller than or equal to that of the side portion of the same. The sealed structure may comprise a highly reliable light-emitting element including a layer containing a light-emitting organic compound provided between a pair of electrodes.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: December 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daiki Nakamura, Yusuke Nishido
  • Patent number: 9214538
    Abstract: A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a FET structure, where multiple channels and multiple gate regions are formed in order to achieve a lower specific on-resistance, and a higher control on the transport properties of the device. No dielectric layer is present between gate electrodes and device channels, decreasing the parasitic capacitance associated with the gate terminal. The fabrication of the device does not require Silicon On Insulator techniques and it is not limited to Silicon semiconductor materials. It can be fabricated as an enhancement or depletion device with much more control on the threshold voltage of the device, and with superior RF performance.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 15, 2015
    Assignee: ETA Semiconductor Inc.
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Patent number: 9202998
    Abstract: A semiconductor light-emitting device, and a method for manufacturing the semiconductor light-emitting device, in which light propagating through a light-emitting layer and reaching an edge surface of a semiconductor film can be extracted to the exterior in an efficient manner. The semiconductor light-emitting device comprises a semiconductor film including a light-emitting layer made from a group III nitride semiconductor. The semiconductor film has a tapered edge surface inclined diagonally with respect to a light extraction surface. The light extraction surface has a relief structure comprising a plurality of protrusions having a shape originating from the crystal structure of the semiconductor film. The average size of the protrusions in a first region in the vicinity of an edge section of the light extraction surface is smaller than the average size of the protrusions in a second region.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 1, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Yasuyuki Shibata, Ji-Hao Liang
  • Patent number: 9166037
    Abstract: A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: October 20, 2015
    Assignee: Sinopower Semiconductor Inc.
    Inventor: Wei-Chieh Lin
  • Patent number: 9159908
    Abstract: A magnetic tunneling junction (MTJ) in an MRAM array is disclosed with a composite free layer having a FL1/FL2/FL3 configuration where FL1 and FL2 are crystalline magnetic layers and FL3 is an amorphous NiFeX layer for improved bit switching performance. FL1 layer is CoFe which affords a high magnetoresistive (MR) ratio when forming an interface with a MgO tunnel barrier. FL2 is Fe to improve switching performance. NiFeX thickness where X is Hf is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. Annealing at 330° C. to 360° C. provides a high MR ratio of 190%. Furthermore, low Hc and Hk are simultaneously achieved with improved bit switching performance and fewer shorts without compromising other MTJ properties such as MR ratio. As a result of high MR ratio and lower bit-to-bit resistance variation, higher reading margin is realized.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: October 13, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Wei Cao, Witold Kula
  • Patent number: 9142412
    Abstract: Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 22, 2015
    Assignee: SOITEC
    Inventors: Christiaan J. Werkhoven, Chantal Arena
  • Patent number: 9130127
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body, first and second electrodes. The stacked structure body includes first and second semiconductor layers and a light emitting layer provided between the second and first semiconductor layers, and has first and second major surfaces. The first electrode has a first contact part coming into contact with the first semiconductor layer. The second electrode has a part coming into contact with the second semiconductor layer. A surface of the first semiconductor layer on a side of the first major surface has a first part having a part overlapping a contact surface with the first semiconductor layer and a second part having a part overlapping the second semiconductor layer. The second part has irregularity. A pitch of the irregularity is longer than a peak wavelength of emission light. The first part has smaller irregularity than the second part.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Yasuo Ohba, Satoshi Mitsugi, Shinji Yamada, Mitsuhiro Kushibe, Kei Kaneko
  • Patent number: 9093604
    Abstract: A method of producing an optoelectronic semiconductor chip having a semiconductor layer stack based on a material system AlInGaP includes preparing a growth substrate having a silicon surface, arranging a compressively relaxed buffer layer stack on the growth substrate, and metamorphically, epitaxially growing the semiconductor layer stack on the buffer layer stack, the semiconductor layer stack having an active layer that generates radiation.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 28, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauβ, Alexander Behres
  • Patent number: 9093432
    Abstract: A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device 10 includes an active region 12, a first insulating layer 13 covering the active region 12, a floating conductor 14 formed on the first insulating layer 13, a second insulating layer 15 formed on the first insulating layer 13 and the floating conductor 14, a bonding pad 18 formed on the second insulating layer 17 and interconnection vias 19, 20 for electrically connecting the active region 12 and the bonding pad 18.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 28, 2015
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Akio Iwabuchi, Hironori Aoki
  • Patent number: 9093379
    Abstract: A silicidation blocking process is provided. In one aspect, a silicidation method is provided. The method includes the following steps. A wafer is provided having a semiconductor layer over an oxide layer. An organic planarizing layer (OPL)-blocking structure is formed on one or more regions of the semiconductor layer which will block the one or more regions of the semiconductor layer from silicidation. At least one silicide metal is deposited on the wafer. The wafer is annealed to react the at least one silicide metal with one or more exposed regions of the semiconductor layer. Unreacted silicide metal is removed. Any remaining portions of the OPL-blocking structure are removed.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9082948
    Abstract: Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 14, 2015
    Assignee: SOITEC
    Inventors: Christiaan J. Werkhoven, Chantal Arena
  • Patent number: 9059402
    Abstract: A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: June 16, 2015
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Toshitsugu Sakamoto, Yuko Yabe, Yukishige Saito, Hiromitsu Hada
  • Patent number: 9048142
    Abstract: The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9041026
    Abstract: A light-emitting unit with small energy loss is provided. Further, a light-emitting unit with high reliability is provided. A light-emitting unit is provided in the following manner: a separation layer including a leg portion and a stage portion, which protrudes over an electrode is formed so that a projected area of the stage portion is larger than that of the leg portion; a layer containing a light-emitting organic compound, an upper electrode of the first light-emitting element, and an upper electrode of the second light-emitting element are formed; and the upper electrode of the first light-emitting element is electrically connected to a lower electrode of the second light-emitting element in a region overlapping with the stage portion of the separation layer.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9024339
    Abstract: The present invention provides a light emitting diode which comprises a substrate, a light emitting layer including an N-type semiconductor layer and a P-type semiconductor layer formed on the substrate, and a wavelength conversion layer formed on the light emitting layer or on the back of the substrate. The wavelength conversion layer is formed of a Group III nitride semiconductor doped with rare earth elements. The rare earth elements include at least one of Tm, Er and Eu. According to a light emitting diode of the present invention, a desired color can be implemented in various ways by converting the wavelength of primary light emitted from a light emitting chip. Thus, the reliability and quality of products can be improved due to the uniform emission of light with a desired color. Further, since the existing semiconductor process can be utilized in the present invention, its fabrication process can be simplified, process cost and time can be reduced, and the compact products can be obtained.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: May 5, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Kyoung Hoon Kim
  • Patent number: 8993358
    Abstract: A method for depositing a layer of phosphor-containing material on a plurality of LED dies includes disposing a template with a plurality of openings on an adhesive tape and disposing each of a plurality of LED dies in one of the plurality of openings of the template. The method also includes disposing a stencil over the template and the plurality of LED dies. The stencil has a plurality of openings configured to expose a top surface of each of the LED dies. Next, a phosphor-containing material is disposed on the exposed top surface of each the LED dies. The method further includes removing the stencil and the template.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 31, 2015
    Assignee: LedEngin, Inc.
    Inventors: Zequn Mei, Xiantao Yan
  • Patent number: 8946759
    Abstract: Disclosed is an organic light emitting display device which prevents or inhibits external gas, such as, oxygen or moisture, from penetrating into a display unit and reinforces a mechanical strength by providing a first sealant and a second sealant. The organic light emitting display device may include: a first substrate; a display unit on the first substrate; a second substrate covering the display unit; a first sealant adhering the first substrate to the second substrate; and a second sealant around the first sealant, the second sealant sealing the first substrate and the second substrate. A filler may be included in the second sealant, and a particle size of the filler may be larger than a gap between the first substrate and the second substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung-Display Co., Ltd.
    Inventors: Jung Woo Moon, Hyun Joon Oh