Abstract: A process for manufacturing a diaphragm unit of a MEMS transducer that includes multiple piezoelectric transducer units, each of the multiple piezoelectric transducer units including at least one electrode layer and at least one piezoelectric layer formed on a carrier includes the step of removing the transducer units from the carrier. At least one of the transducer units that has been removed from the carrier is arranged on a diaphragm and connected to the diaphragm. Moreover, a diaphragm unit made according to the process includes a diaphragm and multiple piezoelectric transducer units arranged on and connected to the diaphragm. Each of the multiple piezoelectric transducer units includes at least one electrode layer and at least one piezoelectric layer formed on a carrier.

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

Abstract: A display device includes a pixel connected to a data line, a data pad connected to the data line, and a first test area. The first test area includes a test control line transmitting a test control signal, a test signal line transmitting a test signal, and a first switch connected to the data pad. The first switch includes a gate electrode connected to the test control line, first and second semiconductor layers overlapping the gate electrode, a source electrode connected to the first and second semiconductor layers, and a drain electrode spaced from the source electrode and connected to the first and second semiconductor layers. The source electrode and the drain electrode are connected to the test signal line and data pad, respectively. One of the first or second semiconductor layers includes an oxide semiconductor and the other of the first or second semiconductor layer includes a silicon-based semiconductor.

Abstract: An electrical device includes a first terminal structured to electrically connect to a power source; a second terminal structured to electrically connect to a load; a voltage sensor electrically connected to a point between the first and second terminals and being structured to sense a voltage at the point between the first and second terminals; a switch electrically connected between the first terminal and the second terminal; and a control unit structured to detect a power quality event in the power flowing between the first and second terminals based on the sensed voltage and to control a state of the switch based on the detected power quality event.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

Abstract: The present invention discloses a display panel and a head mounted device. The display panel includes a substrate and a plurality of micro light emitting units. A first position and a second position are defined at an edge and a center of the substrate respectively. The micro light emitting units are arranged and disposed on the substrate. Any two of the micro light emitting units are disposed at the first position and the second position respectively. Wherein each micro light emitting unit defines a luminating top surface, and a reference angle is defined between each luminating top surface and a reference plane respectively. Wherein the reference angle defined between each luminating top surface and the reference plane gradually decreases from the first position to the second position, and the luminating top surface of the micro light emitting unit located at the second position is parallel to the reference surface.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: A device, such as a light-emitting device, e.g. a laser device, comprising: a plurality of group III-V semiconductor NWs grown on one side of a graphitic substrate, preferably through the holes of an optional hole-patterned mask on said graphitic substrate; a first distributed Bragg reflector or metal mirror positioned substantially parallel to said graphitic substrate and positioned on the opposite side of said graphitic substrate to said NWs; optionally a second distributed Bragg reflector or metal mirror in contact with the top of at least a portion of said NWs; and wherein said NWs comprise aim-type doped region and a p-type doped region and optionally an intrinsic region there between.

Abstract: A light emitting device package including a substrate, a light emitting structure including a plurality of epitaxial stacks sequentially stacked on the substrate configured to emit light having different wavelength bands from each other, the light emitting structure having a light emitting area defined by the epitaxial stacks, a plurality of bump electrodes disposed on the light emitting structure, at least a portion of each bump electrode overlapping with the light emitting area, a molding layer covering a side surface and an upper surface of the light emitting structure, a plurality of fan-out lines disposed on the molding layer and connected to the light emitting structure through the bump electrodes, and an insulating layer disposed on the fan-out lines and exposing a portion of the fan-out lines, in which the exposed portion of the fan-out lines does not overlap with the light emitting area.

Abstract: The present disclosure discloses an organic light emitting display device. The organic light emitting display device includes a substrate, an initializing voltage input line, a first electrode line, a thin film transistor, and an organic light emitting diode arranged on the substrate. The thin film transistor includes a first electrode, a second electrode and a control electrode, and the first electrode is coupled to the first electrode line, the initializing voltage input line is provided in the same layer and is made of the same material as one of the first electrode, the second electrode and the control electrode of the thin film transistor, and an extension direction of the initializing voltage input line is substantially the same as an extension direction of the first electrode line.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.

Abstract: Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A display panel including a circuit board having first pads, a plurality of light emitting devices disposed on the circuit board and having second pads, at least one of the light emitting devices including a repaired light emitting device, and a metal bonding layer bonding the first pads and the second pads, in which the metal bonding layer of the repaired light emitting device has at least one of a thickness and a composition different from that of the metal bonding layer of the remaining light emitting devices.

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.