Patents Examined by Lawrence Tynes, Jr.
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Patent number: 9793218Abstract: In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer metal layer to reach a second terminal of an IC device is formed after forming the outer metal layer.Type: GrantFiled: May 14, 2013Date of Patent: October 17, 2017Assignee: MEIKO ELECTRONICS CO., LTD.Inventors: Mitsuaki Toda, Tohru Matsumoto, Seiko Murata
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Patent number: 9786592Abstract: An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.Type: GrantFiled: October 30, 2015Date of Patent: October 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Hsun-Ying Huang
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Patent number: 9779964Abstract: The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.Type: GrantFiled: June 30, 2016Date of Patent: October 3, 2017Assignee: ZING SEMICONDUCTOR CORPORATIONInventors: Deyuan Xiao, Richard R. Chang
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Patent number: 9773643Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.Type: GrantFiled: June 30, 2016Date of Patent: September 26, 2017Assignee: Lam Research CorporationInventors: Akhil Singhal, Patrick A. Van Cleemput, Martin E. Freeborn, Bart J. van Schravendijk
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Patent number: 9773813Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the array substrate includes depositing an amorphous silicon thin film layer on a base substrate; performing a patterning process on the amorphous silicon thin film layer, so as to form a pattern with multiple small pores at a surface of the amorphous silicon thin film layer. With this method, when a laser annealing treatment of amorphous silicon is performed, the molten silicon after melting fills the space of small pores at a surface of the amorphous silicon thin film layer firstly, thereby avoiding forming a protruded grain boundary that is produced because the excess volume of polysilicon is squeezed.Type: GrantFiled: August 16, 2014Date of Patent: September 26, 2017Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventor: Zhenyu Xie
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Patent number: 9768063Abstract: A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects, wherein the vias are part of a dual damascene structure with trenches and vias is provided. A sealing layer of a first metal or metal alloy that has a low solubility with copper is selectively deposited directly on the copper containing interconnects in at bottoms of the vias, wherein sidewalls of the dielectric layer forming the vias are exposed to the depositing the sealing layer, and wherein the first metal or metal alloy that has a low solubility is selectively deposited to only form a layer on the copper containing interconnects. A via fill of a second metal or metal alloy that has a low solubility with copper is electrolessly deposited over the sealing layer, which fills the vias.Type: GrantFiled: June 30, 2016Date of Patent: September 19, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Lie Zhao
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Patent number: 9758261Abstract: A method of manufacturing a solar cell assembly by providing a substrate; depositing on the substrate a sequence of layers of semiconductor material forming a solar cell; mounting a permanent laminate supporting member with a thickness of 50 microns or less on top of the sequence of layers; utilizing the laminate structure for supporting the epitaxial sequence of layers of semiconductor material forming a solar cell during the processes of removing the substrate and depositing and lithographically patterning a plurality of metal grid lines disposed on the top surface of the first solar subcell, and attaching a cover glass over at least the grid lines of the solar cell.Type: GrantFiled: January 15, 2015Date of Patent: September 12, 2017Assignee: SolAero Technologies Corp.Inventor: Jeffrey Steinfeldt
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Patent number: 9755012Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.Type: GrantFiled: September 2, 2016Date of Patent: September 5, 2017Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
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Patent number: 9748176Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: August 29, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Deniz E. Civay, Erik R. Hosler
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Patent number: 9741693Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.Type: GrantFiled: November 12, 2015Date of Patent: August 22, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Fu Kao, Tsei-Chung Fu, Jing-Cheng Lin
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Patent number: 9741901Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.Type: GrantFiled: July 23, 2014Date of Patent: August 22, 2017Assignee: CBRITE Inc.Inventors: Gang Yu, Chan-Long Shieh, Zhao Chen
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Patent number: 9735084Abstract: In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.Type: GrantFiled: December 11, 2014Date of Patent: August 15, 2017Assignee: Invensas CorporationInventors: Rajesh Katkar, Guilian Gao, Charles G. Woychik, Wael Zohni
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Patent number: 9728520Abstract: An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.Type: GrantFiled: June 21, 2013Date of Patent: August 8, 2017Assignee: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.Inventors: Hong Hu, Qingming Shu, Sai Zhang, Jianjun Zhang, Jiang Liu, Ronghua Pan
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Patent number: 9718098Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.Type: GrantFiled: May 19, 2016Date of Patent: August 1, 2017Assignee: Butterfly Network, Inc.Inventors: Jonathan M. Rothberg, Keith G. Fife, Tyler S. Ralston, Gregory L. Charvat, Nevada J. Sanchez
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Patent number: 9721855Abstract: A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.Type: GrantFiled: December 12, 2014Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Joseph Kuczynski, Phillip V. Mann, Kevin M. O'Connell, Arvind K. Sinha, Karl Stathakis
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Patent number: 9721910Abstract: To shorten a maintenance time of a semiconductor manufacturing apparatus and to improve productivity of a semiconductor manufacturing line. A semiconductor wafer is processed by the semiconductor manufacturing apparatus in which reaction product in the inside of a wafer lift pin hole was removed using a cleaning jig having a return on its tip part.Type: GrantFiled: July 1, 2016Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventor: Yohei Hamaguchi
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Patent number: 9711623Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.Type: GrantFiled: November 10, 2015Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ming-Chyi Liu
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Patent number: 9704807Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Deniz E. Civay, Erik R. Hosler
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Patent number: 9698059Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.Type: GrantFiled: April 15, 2015Date of Patent: July 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tian Choy Gan, Chu-Yun Hsiao, Chia-Fu Hsu
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Patent number: 9691844Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.Type: GrantFiled: November 12, 2015Date of Patent: June 27, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang