Patents Examined by Lawrence Tynes, Jr.
  • Patent number: 9691844
    Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 27, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: In Su Kim, Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
  • Patent number: 9691723
    Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer with a pattern for a first portion of a connector. A first metal layer is plated through the patterned first photoresist layer to form the first portion of the connector which has a first width. A second photoresist layer is formed over the interconnect structure and the first portion of the connector. The second photoresist layer is patterned with a pattern for a second portion of the connector. A second metal layer is plated through the patterned second photoresist layer to form the second portion of the connector over the first portion of the connector. The second portion of the connector has a second width, the second width being less than the first width.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
  • Patent number: 9691754
    Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Mei-Ling Chao, Yi-Chun Chen, Li-Cih Wang, Tien-Hao Tang
  • Patent number: 9680131
    Abstract: An organic light-emitting diode (OLED) panel, a manufacturing method thereof and a display device are provided. The OLED panel comprises: a base substrate, a plurality of OLED units formed on the base substrate, and a reflective structure formed on the base substrate, disposed along the periphery of the OLED units and configured to partially or completely encircle the OLED units. The OLED unit includes an anode layer, an organic emission layer and a cathode layer. The reflective structure is provided with a reflective surface which is configured to reflect light emitted from a side terminal of the organic emission layer to the outside of the OLED panel. The OLED panel can improve the utilization rate of light emitted by the OLED units and hence improve the display quality of the OLED panel.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 13, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Lujiang Huangfu, Wenyu Ma, Lei Shi, Can Zhang, Yinan Liang
  • Patent number: 9680014
    Abstract: A p-type semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first stressor layer and a second stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang
  • Patent number: 9666720
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Patent number: 9666401
    Abstract: The present disclosure may provide a field emission device with an enhanced beam convergence. For this, the device may include a gate structure disposed between a cathode electrode and an anode electrode, wherein the gate structure includes a gate electrode and an atomic layer sheet disposed on the gate electrode, the gate electrode facing an emitter and having at least one aperture formed therein.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: May 30, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: So Ra Park, Yoon Ho Song, Jin Woo Jeong, Jae Woo Kim, Min Sik Shin
  • Patent number: 9659958
    Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 23, 2017
    Assignee: Samsung Elctronics Co., Ltd.
    Inventors: Jung Hoon Lee, Keejeong Rho, Sejun Park, Jinhyun Shin, Dong-Sik Lee, Woong-Seop Lee
  • Patent number: 9647244
    Abstract: An integration equipment for replacing an evaporation material and a use method thereof are provided. The integration equipment includes an evaporation chamber region, a material replacing chamber region, a valve door disposed between the evaporation chamber region and the material replacing chamber region, and for separating the above two regions, a substrate disposed inside the evaporation chamber region, and a material feeding door disposed at a side of the material replacing chamber region away from the valve door. Each of the evaporation chamber region and the material replacing chamber region includes a carrying platform, multiple evaporation sources disposed on the carrying platform, multiple exchanging devices for fixing and delivering the multiple evaporation sources, an independent vacuum-pumping device, and a heating device disposed inside the carrying platform.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: May 9, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jinchuan Li
  • Patent number: 9647236
    Abstract: A packaging method for an organic light emitting display panel, an organic light emitting display panel and a display device are disclosed. The packaging method includes: forming a water/oxygen blocking layer that covers a whole base substrate on the base substrate with an organic light emitting device and a peripheral bonding region formed thereon, etching the water/oxygen blocking layer on the base substrate, so as to at least remove the water/oxygen blocking layer on a connection terminal within the bonding region, and to retain the water/oxygen blocking layer on the organic light emitting device. With the packaging method, an organic light emitting display panel with a narrow frame can be realized.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 9, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seiji Fujino, Qinghui Zeng
  • Patent number: 9640497
    Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Shinzo Ishibe
  • Patent number: 9640461
    Abstract: A power module includes a substrate DMB (Direct Metal Bonded). A novel bridging DMB is surface mounted to the substrate DMB along with power semiconductor device dice. The top metal layer of the bridging DMB has one or more islands to which bonding wires can connect. In one example, an electrical path extends from a module terminal, through a first bonding wire and to a first location on a strip-shaped island, through the island to a second location, and from the second location and through a second bonding wire. The strip-shaped island of the bridging DMB serves as a section of the overall electrical path. Another bonding wire of a separate electrical path passes transversely over the strip-shaped island without any wire crossing any other wire. Use of the bridging DMB promotes bonding wire mechanical strength as well as heat sinking from bonding wires down to the substrate DMB.
    Type: Grant
    Filed: July 31, 2016
    Date of Patent: May 2, 2017
    Assignee: IXYS Corporation
    Inventors: Thomas Spann, Ira Balaj-Loos
  • Patent number: 9640433
    Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark, William Mark Hiatt
  • Patent number: 9634240
    Abstract: Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongchul Park, Byoungjae Bae, Shin-Jae Kang, Eunsun Noh, Kyung Rae Byun
  • Patent number: 9633978
    Abstract: A semiconductor device includes a wiring substrate, a first semiconductor chip flip-chip connected to the wiring substrate, a first underfill resin filled between the wiring substrate and the first semiconductor chip, the first underfill resin including a pedestal portion arranged in a periphery of the first semiconductor chip, a second semiconductor chip flip-chip connected to the first semiconductor chip, and being larger in area than the first semiconductor chip, and a second underfill resin filled between the first semiconductor chip and the second semiconductor chip, the second underfill resin covering an upper face of the pedestal portion of the first underfill resin and a side face of the second semiconductor chip.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 25, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shota Miki
  • Patent number: 9627518
    Abstract: A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Joo Won Park, Kwang Sik Ko
  • Patent number: 9627567
    Abstract: Disclosed is a method for manufacturing a solar cell module (10), said method being provided with: a first step for a first step for manufacturing a laminated body by sequentially stacking and thermocompression-bonding a solar cell (11), sealing material (14), first protection member (12) and second protection member (13); and a second step, which is a step of heating the solar cell (11) of the laminated body, and in which the sealing material (14) is indirectly heated due to a temperature increase of the solar cell (11).
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: April 18, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoto Imada, Keisuke Ogawa, Tasuku Ishiguro
  • Patent number: 9627586
    Abstract: An electroluminescent element includes a first transparent electrode, a second transparent electrode, a light emitting layer sandwiched between the first transparent electrode and the second transparent electrode, a first transparent member formed on a surface of the first transparent electrode opposite to the light emitting layer, and a second transparent member formed on a surface of the second transparent electrode opposite to the light emitting layer, wherein refractive indices of the first transparent electrode and the second transparent electrode are selected such that as seen from the light emitting layer, a reflectance of an interface between the light emitting layer and the first transparent electrode becomes higher than a reflectance of an interface between the light emitting layer and the second transparent electrode, and wherein a refractive index of the first transparent member is set to be higher than a refractive index of the second transparent member.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 18, 2017
    Assignee: KONICA MINOLTA, INC.
    Inventors: Kou Osawa, Mitsuru Yokoyama
  • Patent number: 9620508
    Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 11, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Kumano
  • Patent number: 9620639
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 11, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia Hossain, Gordon M. Grivna