Abstract: A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.

Abstract: Systems, methods, applications and uses for trans-radix quantum information processing elements are disclosed.

Abstract: Embodiments described herein relate to a system, software, and a method of using the system to edit a design to be printed by a lithography system. The system and methods utilize a server of a maskless lithography device. The server includes a memory. The memory includes a virtual mask file. The virtual mask file includes cells and the cells include sub-cells that form one or more polygons. The server further includes a controller coupled to the memory. The controller is configured to receive a replacement table. The replacement table includes instructions to replace the cells of the virtual mask file. The controller is further configured to replace the cells with replacement cells according to the replacement table to create an edited virtual mask file.

Abstract: Inductive energy emitter/receiver including a planar-shaped magnetic core with two opposed main surfaces is provided having at least one conductive coil wound around an axis perpendicular to the main surfaces of the planar-shaped magnetic core, said the conductive coil being overlapped to one of the main surfaces of the magnetic core; an inductor casing being attached to the planar-shaped magnetic core and at least one conductive coil. The inductor casing is at least partially made of flexible polymer bonded soft magnetic material, and the planar-shaped magnetic core is a made of a plurality of flexible elongated partial cores, forming a flexible planar shaped magnetic core.

Abstract: A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

Abstract: Predicting power usage of a chip may include receiving placement data describing a placement, within the chip, of a plurality of logical components of the chip; providing the placement data as an input to a neural network; and determining, by the neural network, based on the placement data, a predicted power usage of the chip.

Abstract: Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing paths, is modified from a first value to a second value, based on the path margin. A design metric relating to the IC design is updated based on the modified second slack. The IC design is configured to be used to fabricate an IC.

Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.

Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Abstract: A method for sample scheme generation includes obtaining measurement data associated with a set of locations; analyzing the measurement data to determine statistically different groups of the locations; and configuring a sample scheme generation algorithm based on the statistically different groups. A method includes obtaining a constraint and/or a plurality of key performance indicators associated with a sample scheme across one or more substrates; and using the constraint and/or plurality of key performance indicators in a sample scheme generation algorithm including a multi-objective genetic algorithm. The locations may define one or more regions spanning a plurality of fields across one or more substrates and the analyzing the measurement data may include stacking across the spanned plurality of fields using different respective sub-sampling.

Abstract: An air cooled oil-free centrifugal chiller system and method, the system comprising at least one AC condenser fan; at least one solar panel; at least one AC/DC convertible fan connected to the at least one solar panel; and a controller configured to determine when sufficient DC power is available and activating the at least one AC/DC convertible fan when sufficient DC power is available, and when DC power is not sufficient, activating the at least one AC condenser fan.

Abstract: Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.

Abstract: A power device including a housing, charging circuitry, and discharge circuitry. The housing defining a first support operable to support a first battery pack, and a second support operable to support a second battery pack. The charging circuitry electrically is connected to the first battery pack and the second battery pack in a parallel-type connection. The charging circuity is configured to simultaneously charge the first battery pack and the second battery pack. The discharge circuitry is electrically connected to the first battery pack and the second battery pack. The discharge circuitry is configured to electrically connect the first battery pack and the second battery pack in a series-type connection during a discharge.

Abstract: A method for determining a training pattern in a layout patterning process. The method includes generating a plurality of features from patterns in a pattern set; grouping the patterns in the pattern set into individual groups based on similarities in the plurality of generated features; and selecting representative patterns from the individual groups to determine the training pattern. In some embodiments, the method is a method for training a machine learning model in a layout patterning process. The method may include, for example, providing representative patterns from the individual groups to the machine learning model to train the machine learning model to predict a continuous transmission mask (CTM) map for optical proximity correction (OPC) in the layout patterning process.

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.