Abstract: A method is provided for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

Abstract: Operating systems of virtual machines periodically issue diagnostic instructions during the normal operation. A virtual machine control monitor selects the earliest one of monitoring times for virtual machines and sets it in the clock facility in a bare machine. If the monitor receives the diagnostic command from a virtual machine before expiration of the monitoring time, it re-sets the clock facility. Otherwise, the monitor issues a machine check interrupt command to the virtual machine in which the monitoring time has expired.

Abstract: An emulator for a single-chip microcomputer comprises a single-chip microcomputer and an emulation memory which are coupled to each other through a common adress/data bus. A counter is coupled to the address/data bus to receive an address information from the microcomputer and adapted to output an address to the memory. The microcomputer operates to supply an address information on the address/data bus immediately after execution of a branch instruction so that the address information is preset in the counter, and in a program fetch operation the microcomputer generates a program fetch signal to the counter so as to cause the counter to output its content to the memory as an address and also to increment its content.