Abstract: An easily-installed cover plate for hiding the face of sockets by covering an electrical outlet, including the face of the sockets. The cover plate is mounted over the receptacle and has apertures for plug blades. In the preferred embodiment, the cover plate is rectangularly shaped to cover a duplex receptacle, having apertures to receive plug blades, a center hole for receiving a screw which secures the cover plate over the duplex receptacle and a thickness at the apertures for receiving plug blades of not more than 0.075 inches.

Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Abstract: A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.

Abstract: Connection terminal (10) according to the present invention includes a tab part and not smaller than four pinching plates (12) that hold an aluminum electric wire. Pinching plates (12) each include first slit (13) and contact surfaces (14). First slit (13) has a first open end located in one side of the slit, and a first tip located in the other side. The aluminum electric wire is inserted into first slit (13). Contact surfaces (14) are in contact with the aluminum electric wire that is press-fitted into first slit (13). A contact area in which contact surfaces (14) are in contact with a core wire is an area of 100% to 200% of a radial cross-sectional area of the core wire.

Abstract: Provided is a package of a light emitting diode. The package according to an embodiment includes a base layer, a light emitting diode chip on the base layer, a lead frame electrically connected to the light emitting diode chip, a reflective coating layer directly on the lead frame, and a molding material covering the light emitting diode chip in a predetermined shape.

Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.

Abstract: A light emitting device includes a substrate layer, a first electrode layer, a light emitting layer, and a patterned second electrode layer. The patterned second electrode layer includes a periodic grating structure having a grating period ?g less than or equal to 200 nm and the patterned second electrode layer and the light emitting layer are separated by at most 100 nm.

Abstract: LED assemblies and related LED light bulbs. An LED assembly has a flexible, transparent substrate, an LED chip on the first surface and electrically connected to two adjacent conductive sections, a first wavelength conversion layer, formed on the first surface to substantially cover the LED chip, and a second wavelength conversion layer formed on the second surface. The flexible, transparent substrate has first and second surfaces opposite to each other, and several conductive sections, which are separately formed on the first surface.

Abstract: Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.

Abstract: A heat sink system to conduct heat away from a printed circuit board assembly is provided. The heat sink system includes a chassis, a chassis cover, at least one thermally conductive block underlaying a high-heat section of the printed circuit board assembly, a plurality of thermally conductive through-rods, and at least one thermally conductive notch-rod associated with a respective thermally conductive block. The at least one thermally conductive block is in thermal contact with a portion of the chassis. The plurality of thermally conductive through-rods and at least one thermally conductive notch-rod each have a first end and a second end. The through-rods are positioned in holes formed in the printed circuit board. The notch-rods are positioned in a notch formed in the printed circuit board assembly. The first ends thermally contact the thermally conductive block and the second ends thermally contact the chassis cover.

Abstract: The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.

Abstract: A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.

Abstract: An easily-installed cover plate for hiding the face of sockets by covering an electrical outlet, including the face of the sockets. The cover plate is mounted over the receptacle and has apertures for plug blades. In the preferred embodiment, the cover plate is rectangularly shaped to cover a duplex receptacle, having apertures to receive plug blades, a center hole for receiving a screw which secures the cover plate over the duplex receptacle and a thickness at the apertures for receiving plug blades of not more than 0.075 inches.

Abstract: An organic light-emitting display device comprising a substrate; an insulating layer disposed on the substrate; a plurality of bottom electrodes arranged on the insulating layer in a matrix pattern defining a plurality of intersecting rows and columns; an organic layer disposed on each of the bottom electrodes; a top electrode disposed on the organic layer; and a plurality of wiring lines adjacent to the first bottom electrode, the wiring lines being formed on the insulating layer placed between the rows of the bottom electrodes.

Abstract: A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.