Patents Examined by Leslie Pilar Cruz
  • Patent number: 10461192
    Abstract: A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Eun-Hyun Kim, Sang-Won Shin, Eun-Young Lee
  • Patent number: 10374087
    Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Won Kim, Jae-Kyu Lee
  • Patent number: 10340369
    Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 10290724
    Abstract: A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source region includes an inner portion of the first semiconductor material and an outer portion of a second semiconductor material overlying a top surface and side surfaces of the inner portion. The drain region includes an inner portion of the first semiconductor material and an outer portion of the second semiconductor material overlying a top surface and side surfaces of the inner portion.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 14, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xinyun Xie
  • Patent number: 10283521
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device includes source select lines, word lines, drain select lines, and a bit line stacked on a substrate in which a first cell string region and a second cell string region are defined; channel layers and memory layers vertically passing through the source select lines, the word lines, and the drain select lines in each of the first cell string region and the second cell string region; and a common source line vertically passing through the source select lines, the word lines, and the drain select lines at centers of the first cell string region and the second cell string region, and extended to a lower side of the source select lines.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventor: Min Sik Jang
  • Patent number: 10256334
    Abstract: A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the conducting channel. A control contact is located outside of a region between the input and output contacts, and can be used to adjust the switch between on and off operating states. The switch can be implemented as a radio frequency switch in a circuit.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: April 9, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 10199300
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiaki Goto
  • Patent number: 10141408
    Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 27, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Kunpeng Jia, Yajuan Su, Huilong Zhu, Chao Zhao
  • Patent number: 10141478
    Abstract: A light emitting device including a substrate, a first conductive layer on the substrate, a second conductive layer on the first conductive layer, a metal layer on the second conductive layer, a light emitting structure on the metal layer and the second conductive layer, the light emitting structure including a first semiconductor layer containing AlGaN, an active layer, and a second semiconductor layer containing AlGaN, a first electrode on the light emitting structure, and a passivation layer disposed on a side surface of the light emitting structure.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 27, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Hwan Hee Jeong, Kwang Ki Choi, June O Song, Sang Youl Lee
  • Patent number: 10134631
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 10134759
    Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 20, 2018
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, James Kuss
  • Patent number: 10128414
    Abstract: A chip substrate includes: a plurality of conductive layers horizontally stacked and constituting the chip substrate; a plurality of insulation layers alternately with the conductive layers and electrically separating the conductive layers; a lens insert comprising a groove having a predetermined number of edges on the upper surface of the chip substrate and having a cross-section wherein an arc is formed at the region where the extended edges meet; a cavity comprising a groove reaching down to a predetermined depth towards the area accommodating the insulation layer within the internal region of the lens insert; and a plurality of joining grooves formed on the surface of the lens insert. Thus, the lens to be inserted also can be formed to be a shape comprising straight lines so that the manufacturing process of the lens to be inserted into the chip substrate can be further simplified.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 13, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Seung Ho Park, Tae Hwan Song
  • Patent number: 10109754
    Abstract: Disclosed is at least one embodiment of an infrared (IR) photovoltaic (PV) detector, comprising a IV-VI Lead (Pb)-salt layer disposed on a substrate and a charge-separation-junction (CSJ) structure associated with the IV-VI Pb-salt layer, wherein the CSJ structure comprises a plurality of element areas disposed upon or within the IV-VI Pb-salt layer, wherein the plurality of element areas are spaced apart from each other. Each element area may be connected to a first Ohmic contact thereby forming a plurality of interconnected first Ohmic contacts, and a second Ohmic contact may be disposed upon a portion of the IV-VI Pb-salt layer. In another non-limiting embodiment, a PV detector, comprising a heterojunction region that comprises at least one IV-VI Pb-salt material layer coupled to at least one non-Pb-salt layer, wherein the at least one IV-VI Pb-salt layer and the at least one non-Pb-salt layer form a p-n junction or Schottky junction with a type II band gap alignment.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 23, 2018
    Assignee: The Board of Regents of the University of Oklahoma
    Inventor: Zhisheng Shi
  • Patent number: 10096595
    Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain, Anurag Mittal, Sangmoon Kim
  • Patent number: 10090287
    Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10072291
    Abstract: The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: September 11, 2018
    Assignee: UNIVERSITY OF HAWAII
    Inventor: James Holm-Kennedy
  • Patent number: 10050150
    Abstract: A thin-film transistor includes: an oxide semiconductor layer having a channel region, a source region, and a drain region; a gate insulating layer disposed above the oxide semiconductor layer; a gate electrode disposed at a position that is above the gate insulating layer and opposing the channel region; and a metal oxide layer stacked on the oxide semiconductor layer and in contact with the source region and the drain region. The metal oxide layer includes, as a main component, an oxide of a second metal whose bond dissociation energy with oxygen is greater than that of a first metal included in the oxide semiconductor layer. A first concentration ratio of oxygen to the second metal in an interface layer between the metal oxide layer and the oxide semiconductor layer is greater than a second concentration ratio of the same in a bulk layer of the metal oxide layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 14, 2018
    Assignee: JOLED INC.
    Inventors: Emi Kobayashi, Arinobu Kanegae, Yusuke Fukui
  • Patent number: 10050053
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Merii Inaba
  • Patent number: 10050173
    Abstract: A light emitting device includes a semiconductor light emitting unit and a light-transmitting substrate. The light-transmitting substrate includes an upper surface having two long sides and two short sides and a side surface, and the semiconductor light emitting unit is disposed on the upper surface. The side surface includes two first surfaces, two second surfaces, and rough micro-structures. Each of the first surfaces is connected to one of the long sides of the upper surface, and each of the second surfaces is connected to one of the short sides of the upper surface. The rough micro-structures are formed on the first surfaces and the second surfaces, a covering rate of the rough micro-structures on each of the first surfaces is greater than or equal to a covering rate of the rough micro-structures on each of the second surfaces. A manufacturing method of the light emitting device is also provided.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 14, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Jing-En Huang, Kai-Shun Kang, Yu-Chen Kuo, Fei-Lung Lu, Teng-Hsien Lai
  • Patent number: 10035703
    Abstract: A micro-electromechanical pressure transducer formed from a silicon die centers itself on a pedestal, formed from either a metal or a dielectric, by applying a predetermined amount of liquid epoxy adhesive to the square, top surface of the pedestal and allowing the liquid adhesive to distribute itself over the top surface. A MEMS die placed atop the liquid adhesive is centered on the top surface by surface tension between sides of the die and the top surface.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 31, 2018
    Assignee: Continental Automotive Systems, Inc.
    Inventor: Joe Pin Wang