Patents Examined by Linda J. Fleck
  • Patent number: 5456206
    Abstract: A method for growing a thin InGaAs or InAlAs layer with heavy lattice mismatching on a GaAs substrate by a MOCVD process is described. A first material gas is injected by a MOCVD process to grow a buffer layer on a GaAs substrate to a prescribed thickness. After stopping the injection of the first material gas for a few seconds, a second material gas containing a column III element is injected at a prescribed temperature. A third material gas containing a column V element is injected to grow, on the buffer layer, a thin metallic layer of a binary compound containing the column III element of a high concentration to a thickness of 2 nm or less. After a prescribed time from the injection of the third material gas, In and Ga gases or In and Al gases, mixed in the prescribed proportion are injected in an atmosphere of said third material gas to grow a thin InGaAs or InAlAs layer on the thin metallic layer.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: October 10, 1995
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Bun Lee, Mee-Young Yoon, Jong-Hyeob Baek
  • Patent number: 5453398
    Abstract: Disclosed is a fabricating method of a quantum wire laser diode, comprising the steps of preparing a GaAs substrate; sequentially forming n-type epitaxial layers and a first photoresist layer on the GaAs substrate; removing a portion of the intrinsic GaAs layer by using a first etching solution, and then removing the photoresist layer; wet-etching away a portion of the intrinsic AlAs layer in the vicinity of the opening by using a second etching solution; growing a quantum structure in the molecular beam epitaxy apparatus to form a multiple quantum well on the intrinsic GaAs layer and form a quantum wire on the n-type energy band slope layer through the opening; removing the quantum well, the intrinsic GaAs layer and the intrinsic AlAs layer simultaneously by using a third etching solution; sequentially forming a p-type energy band slope layer, a p-type cladding layer and a p.sup.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: September 26, 1995
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hae-Gwon Lee, Jae-Jin Lee, Bo-Woo Kim
  • Patent number: 5451541
    Abstract: An insulating film is provided on a single crystal silicon layer of a SOI substrate, and a first groove for device isolation and a second groove for thickness measurement are formed to expose a surface of a silicon substrate of the SOI substrate. Then, the first and second grooves are filled with a filling film, and the filling film is etched back, so that the first groove is still filled with the filling film, while the filling film which have filled the second groove is removed to expose the surface of the silicon substrate, because the second groove has a width larger than that of the first groove.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: September 19, 1995
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Sugiyama
  • Patent number: 5445997
    Abstract: A patterning method which comprises forming a photosensitive inorganic semiconductor layer on a semiconductor substrate and irradiating the photosensitive inorganic semiconductor layer which is kept in contact with an electrolyte with light of energy greater than the band gap of the semiconductor layer. Thus, a portion of the semiconductor layer which has been exposed or unexposed to light is dissolved into the electrolyte, thereby producing a desired pattern on the substrate.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: August 29, 1995
    Assignees: Matsushita Electric Industrial Co., Ltd., Akira Fujishima
    Inventors: Akira Fujishima, Shigeo Kondo
  • Patent number: 5445991
    Abstract: A method for fabricating a silicon diaphragm comprises the steps of preparing an n-type silicon substrate; diffusing n.sup.+ impurities in the silicon substrate to form an n.sup.+ diffusion region in a part of the upper wall thereof; growing an n-type silicon epitaxial layer thereon; forming a through-hole in the n-type silicon epitaxial layer to expose a part of the n.sup.+ diffusion region; performing an anodic reaction in an HF solution to make the n.sup.+ diffusion region a porous silicon layer; etching the porous silicon layer to form an air-gap;and, sealing the through-hole.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: August 29, 1995
    Assignees: Kyungdook National University Sensor Technology Research Center, Mando Machinery Corporation
    Inventor: Jong H. Lee
  • Patent number: 5441912
    Abstract: This invention provides a method of manufacturing laser diodes having a high efficiency and a high optical output and showing an excellent temperature-dependent performance at a high yield. The method comprises steps of forming a mesa on a p-type compound semiconductor substrate 1 by sequentially arranging at least a p-type compound semiconductor cladding layer 2, an active layer 3 and an n-type compound semiconductor compound layer 4, burying the lateral sides of said mesa with a p-type compound semiconductor buried layer 6 and an n-type compound semiconductor current blocking layer 7, removing said n-type compound semiconductor current blocking layer 7 partly at areas contacting each of the lateral sides of said mesa to partly expose the p-type compound semiconductor buried layer 6 in the vicinity of said mesa and then burying the remaining space with a p-type compound semiconductor current blocking layer 8.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: August 15, 1995
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Naoki Tsukiji, Hiroyuki Aida
  • Patent number: 5436195
    Abstract: In a method of fabricating an integrated semiconductor light modulator and laser device, a semiconductor layer having first and second regions of different crystal compositions is produced on each chip region of a semiconductor wafer by a selective crystal growth using, as a mask, a dielectric film having a prescribed pattern. Thereafter, a semiconductor laser and a light modulator that modulates laser light emitted from the semiconductor layer are produced in a first semiconductor region and a second semiconductor region, respectively, of each chip region. In this method, the shape of the dielectric mask pattern and the shape of the opening of the mask pattern on each chip region is symmetrical with the dielectric mask pattern and opening of an adjacent chip region along the optical waveguide direction of the semiconductor laser.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: July 25, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Kimura, Yutaka Mihashi, Katuhiko Goto, Takushi Itagaki
  • Patent number: 5436193
    Abstract: A method of fabricating monolithic arrays having closely spaced laser stripes which output laser beams with large, but well-controlled, wavelength separations. The method begins by depositing on a substrate a lower cladding layer and a plurality of stacked active regions with different bandgaps and which are separated by etch stop layers. The stacked active regions are stacked in order of decreasing energy bandgaps as one moves away from the substrate. One or more stacks are then formed by etching one or more active layers using a patterned mask and the etch stop layers such that the topmost active region that remains in each stack has a bandgap which corresponds to the desired laser beam color from that stack. An upper cladding layer is then grown over the exposed surfaces. Beneficially, a lateral confinement region is then created around the stacks (such as by using impurity-induced layer disordering).
    Type: Grant
    Filed: November 2, 1993
    Date of Patent: July 25, 1995
    Assignee: Xerox Corporation
    Inventors: Kevin J. Beernink, Robert L. Thornton
  • Patent number: 5436191
    Abstract: In situ removal of selected or patterned portions of quantum well layers is accomplished by photo induced evaporation enhancement to form quantum wire, patterned quantum wire and multiple quantum wires in a semiconductor structure.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: July 25, 1995
    Assignee: Xerox Corporation
    Inventors: Thomas L. Paell, John E. Epler
  • Patent number: 5436192
    Abstract: The technique of induced evaporation enhancement is used in MOCVD to accomplish geometrical variations via atomic level removal or thinning or negative growth techniques in situ during or after epitaxial growth thereby varying optical and electrical properties of fabricated semiconductor structures during growth. Among the structures capable of being fabricated are three dimensional buried heterostructures, transparent window lasers, multiple wavelength array lasers, index guided and antiguided mechanisms and transparent optical waveguide structures for optical signal coupling in integrated circuitry.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: July 25, 1995
    Assignee: Xerox Corporation
    Inventors: John E. Epler, Thomas L. Paoli
  • Patent number: 5434110
    Abstract: Methods of chemical vapor deposition (CVD) are disclosed wherein high quality films are deposited on patterned wafer substrates. In the methods, a patterned wafer is rotated about an axis thereof in a CVD reaction chamber and reactant gases are directed into the reaction chamber and toward the patterned wafer substrate in a direction generally perpendicular to the plane of rotation of the wafer. The reaction chamber is maintained at a suitable pressure and the wafer is heated to a suitable temperature whereby a high quality film is deposited by CVD on the patterned wafer substrate. The process is applicable to deposit elemental films, compound films, alloy films and solid solution films, and is particularly advantageous in that high film deposition rates and high reactant conversion rates are achieved.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: July 18, 1995
    Assignee: Materials Research Corporation
    Inventors: Robert F. Foster, Helen E. Rebenne
  • Patent number: 5432123
    Abstract: A monolithically integrated electroabsorption modulator/optical amplifier is described which is prepared using a lateral bandgap control technique with a planar III-V compund semiconductor substrate. The described device evidences a bandgap shift in excess of 60 nanometers, so indicating its applicability for integration of modulators and lasers or amplifiers. The device is fabricated by atmospheric pressure metal organic condensed vapor deposition growth of gallium indium arsenise/gallium indium aresenide phosphide strained quantum wells on ridges deposited on the substrate.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: July 11, 1995
    Assignee: AT&T Corp.
    Inventors: Andrew G. Dentai, Fumio Koyama, Kang-Yi Liou
  • Patent number: 5432120
    Abstract: For producing a laterally limited, single-crystal region on a substrate, for example the collector of a bipolar transistor or the active region of a MOS transistor, a mask layer having an opening is produced on the surface of a substrate. The surface of the substrate is exposed within the opening. The cross-section of the opening parallel to the surface of the substrate at the surface of the substrate projects laterally beyond that cross-section at the surface of the mask layer. The sidewall of the opening proceeds essentially perpendicularly relative to the surface of the substrate in the region of the surface of the mask layer and has a step-shaped profile in cross-section perpendicularly relative to the surface of the substrate. The single-crystal region is formed by selective epitaxy within the opening.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: July 11, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Meister, Reinhard Stengl
  • Patent number: 5431127
    Abstract: A method of manufacturing semiconductor particles (30) of uniform mass. A template (12) is used to meter out uniform mass piles (28) of semiconductor feedstock upon a refractory layer (14). These piles (28) of semiconductor feedstock are then melted briefly to obtain semiconductor particles (30) of uniform mass. Silica is the preferred refractory layer, and is separated from the particles after the melt procedure. Subsequent melt procedures can be implemented to ultimately obtain perfect spheres of the semiconductor material. The present invention is well suited for forming semiconductor spheres to be implemented in photovoltaic solar cells. Semiconductor grade or metallurgical grade feedstock can be implemented to obtain particles of high purity. High yields of uniformly massed spheres can be obtained to produce high efficiency photovoltaic cells at a moderate cost.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: July 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Gary D. Stevens, Harvey L. Conklin
  • Patent number: 5427976
    Abstract: In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: June 27, 1995
    Assignee: NEC Corporation
    Inventors: Risho Koh, Atsushi Ogura
  • Patent number: 5426060
    Abstract: A method of inspecting and a method of manufacturing image sensors formed on a surface of a semiconductor wafer. A semiconductor wafer is provided having image sensors formed on its surface. Grooves are cut at boundaries between image sensors to be inspected, so that each groove has a depth that is smaller than the thickness of the semiconductor wafer. The grooves are cut in the boundaries between the image sensors so that photoN sensing carriers generated in the boundary regions, that are not generated by the image sensor being inspected, do not affect the inspection of the image sensor. The characteristics of the image sensors are inspected before cutting through the semiconductor wafer to form individual image sensors. Thus, in accordance with the present invention, the electrical characteristics of the image sensors can be accurately ascertained either before or after separation from the semiconductor wafer.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: June 20, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Satoshi Machida, Hiroshi Mukainakano, Masahiro Yokomichi, Masato Higashi
  • Patent number: 5424242
    Abstract: A method for making an optical amplifier according to which a stack of the following layers is made by epitaxy: a first optical guiding layer; a first chemical attack barrier layer; a second optical guiding layer; a second chemical attack barrier layer; an active layer; a confinement layer; and a contact layer. Then at least one amplifier element followed by an optical guide located beneath this amplifier element are etched in these layers. The method can be applied to the making of optoelectronic devices such as modulators, change-over switches, distributors, etc.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: June 13, 1995
    Assignee: Thomson-CSF
    Inventors: Robert Blondeau, Yannick Bourbin, Daniel Rondi
  • Patent number: 5422306
    Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: June 6, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
  • Patent number: 5421910
    Abstract: An intermetallic compound semiconductor thin film comprises thin film made of the III-V group intermetallic compound InTlSb. Preferably, the thin film is grown by a vapor phase MOCVD method.
    Type: Grant
    Filed: February 10, 1994
    Date of Patent: June 6, 1995
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5418190
    Abstract: A method of fabricating a semiconductor electro-optical device in which a cleaving apparatus is used to separate the wafer into bars of semiconductor material by striking the wafer from the epitaxial side, directly beneath the substrate side scribe mark. A series of angularly shaped trenches are etched across the epitaxial side of the semiconductor bars to permit bar separation into individual devices that allows a plurality of bars to be processed simultaneously.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: May 23, 1995
    Assignee: AT&T Corp.
    Inventors: Mark B. Cholewa, John W. Osenbach, Bryan P. Segner