Abstract: According to some examples, systems and methods are provided for voltage sampling using one or more analog-to-digital converters (ADCs) to sense divided portions of a sampled voltage (e.g., of an output signal), using the one or more analog-to-digital converters to provide a plurality of digital values representative of those divided portions, and combining the plurality of digital values to produce a total digital value representative of the sampled voltage. Such systems and methods can achieve a high resolution for the total digital value while permitting use of ADCs that have a resolution lower than would otherwise be required to achieve the high resolution.

Abstract: The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

Abstract: Deterioration in audio quality is inhibited in a device which records audio and stretches a reproduction time period. A sampling processing unit performs processing of sampling audio in a predetermined period at a sampling rate higher than a predetermined sampling rate to generate audio data as high-resolution audio data, and processing of sampling audio outside the predetermined period at the predetermined sampling rate to generate audio data as normal audio data. Also, a reproduction time conversion unit stretches the reproduction time period of the high-resolution audio data.

Abstract: An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuitry. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.

Abstract: Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed.

Abstract: A compression algorithm based on Huffman coding is disclosed that is adapted to be readily implemented using VLSI design. A data file may be processed to replace duplicate data with a copy commands including an offset and length, such as according to the LV algorithm. A Huffman code may then be generated for parts of the file. The Huffman code may be generated according to a novel method that generates Huffman code lengths for literals in a data file without first sorting the literal statistics. The Huffman code lengths may be constrained to be no longer than a maximum length and the Huffman code may be modified to provide an acceptable overflow probability and be in canonical order. Literals, offsets, and lengths may be separately encoded. The different values for these data sets may be assigned to a limited number of bins for purpose of generating usage statistics used for generating Huffman codes.

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

Abstract: An encoding apparatus reads text data of an encoding target, encodes each character or word in the text data of the encoding target by using a bit map type index in which an appearance position is associated with each of the encoded characters or words, appearing on the text data of the encoding target, as bit map data, and updates the bit map type index with respect to the encoded character or word.

Abstract: Example data compressors disclosed herein include a hash unit to identify a hash table entry matching a hash index determined for a current position of a data stream undergoing data compression, the hash table entry identifying one or more prior positions of the data stream. Disclosed example data compressors also include a match engine to perform data matching based on the current position of the data stream and the one or more prior positions of the data stream to determine a primary match result and a backward match result for the current position of the data stream. Disclosed example data compressors further include a results evaluator to determine an output match result for the current position of the data stream based on the primary match result for the current position of the data stream and a backward match result determined for a subsequent position of the data stream.

Abstract: Systems, methods, and circuitries are provided to control a gain setting in an analog-to-digital converter (ADC) that converts an analog signal to a digital signal based on a reference voltage. Temperature compensation circuitry includes a temperature gain correction circuitry and a combination circuitry. The temperature gain correction circuitry is configured to determine a correction term based on a temperature that affects the reference voltage. The combination circuitry is configured to combine the correction term with a calibration gain value to generate a corrected calibration gain value and provide the corrected calibration gain value to the ADC to control the gain setting.

Abstract: Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Abstract: A method of driving a network device for outputting signals to a physical network transmission medium. The network device includes a DAC circuit that comprises a plurality of digital-to-analog conversion units. Each digital-to-analog conversion unit includes a first auxiliary current source and a second auxiliary current source. The method includes the steps of: detecting a length of the physical network transmission medium; generating a control signal according to the length; generating a bias signal according to the control signal; applying the bias signal to the first auxiliary current source and the second auxiliary current source to control the currents of the first auxiliary current source and the second auxiliary current source.

Abstract: A device that includes a node engine configured to emulate a first node, a second node, and a third node. The first node is configured to receive a first correlithm object, fetch a second correlithm object based on the first correlithm object, and output the second correlithm object to the second node and the third node. Each correlithm object is a point in an n-dimensional space represented by a binary string. The second node is configured to receive the second correlithm object, fetch a third correlithm object based on the second correlithm object, and output the third correlithm object to the third node. The third node is configured to receive the second correlithm object, receive the third correlithm object, fetch a fourth correlithm object based on the second correlithm object and the third correlithm object, and output the fourth correlithm object.

Abstract: A device that includes a master boss and a slave boss. The slave boss is configured to iteratively send execute and output commands to a first plurality of nodes implemented by a node engine identified in a first boss table in response to receiving an execute command from the master boss. The master boss is configured to iteratively send execute and output commands to the slave boss and a second plurality of nodes implemented by the node engine identified in a second boss table. Each node is configured to receive a first correlithm object, fetch a second correlithm object based on the first correlithm object in response to receiving an execute command, and output the second correlithm object in response to receiving an output command.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.

Abstract: Aspects of the subject disclosure may include, for example, a waveguide including a plurality of devices that facilitate generating scattered electromagnetic waves from electromagnetic waves propagating on a surface of a transmission medium. The scattered electromagnetic waves combine to generate a wireless signal having a directionality based on a separation between plurality of devices and a wavelength of the electromagnetic waves. Other embodiments are disclosed.

Abstract: The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method enabling achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings.

Abstract: A thin-film transistor (TFT) device may include a data line and a gate line formed on a base substrate, a TFT connected to the data line and the gate line, and a magnetic field antenna spaced apart from the data line and the gate line on the base substrate. The magnetic field antenna may be connected to the TFT and configured to transmit and receive a signal to and from the TFT or to control a driving of the TFT.

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.