Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: An analog-to-digital converter (“ADC”) includes receiving an analog input voltage signal, converting the analog input voltage signal to a first digital value and an analog residue signal, converting the analog residue signal to a time value representing the analog residue signal, and converting the time value to a second digital value. The first digital value and the second digital value are combined into a digital output signal representing the analog input voltage signal.

Abstract: An A/D converter is provided with: an integrator that includes an operational amplifier provided with a first input terminal and an output terminal, and an integration capacitor; a quantizer that outputs a quantization result obtained by quantizing an output signal from the operational amplifier; and a DAC that is connected to the first input terminal and determines DAC voltage. The integrator has a feedback switch between the integration capacitor and the output terminal of the operational amplifier. An analog signal as an input signal is inputted between the integration capacitor and the feedback switch. The integration capacitor samples the analog signal. The quantizer performs the quantization based on the output of the operational amplifier. The DAC sequentially subtracts electric charge accumulated in the integration capacitor to thereby change the analog signal to a digital value.

Abstract: A high-speed analog-to-digital converter can produce a digital signal representative of an analog input electrical signal. An optical amplitude modulator can modulate an input optical pulse train using the analog input electrical signal. An optical splitter can split the modulated optical pulse train into a plurality of modulated optical pulse trains. Optical path delays can stagger in time the modulated optical pulse trains to form a plurality of time-staggered modulated optical pulse trains. Demodulators can detect and filter the time-staggered modulated optical pulse trains to form a respective plurality of time-averaged voltages. Analog-to-digital converters can output a respective plurality of digital time series representative of the respective time-averaged voltages. An interleaver can aggregate the plurality of digital time series to form the digital signal, which has a sample rate greater than a repetition rate of the input optical pulse train.

Abstract: A semiconductor device capable of detecting a minute current with high accuracy is provided. The semiconductor device includes a first circuit, a second circuit, a first transistor, and a second transistor. A first analog signal is input to the first circuit via the first transistor. A second analog signal is input to the first circuit via the second transistor. The first analog signal includes a value of a first current. The second analog signal includes a value of a second current. The first circuit is capable of converting the first analog signal into a first digital signal. The second circuit is capable of generating a second digital signal based on the first digital signal. The first circuit is capable of converting the second analog signal into a third digital signal based on the second digital signal. The first or second transistor includes an oxide semiconductor in a channel.

Abstract: Modular serializer and deserializer circuits convert a data input in a variety of applications. The serializer includes an array of cells that receive a parallel data input and transfer the word, row by row, to an output buffer that generates a corresponding serial data output. The deserializer includes an input buffer that receives a serial data input and transfers partial words sequentially through an array of cells. When the word fully occupies the cells, the array transmits the word as a parallel data output. A modular clock operates to clock the modular serializer and deserializer.

Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.

Abstract: A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an MSB, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an LSB and a next to bit of the LSB.

Abstract: A method includes receiving multiple bits to be transmitted. The method also includes applying a first binary alphabet polar code to a first subset of the multiple bits to generate first encoded bits. The first encoded bits are associated with a first bit level of a multilevel coding scheme. The method further includes generating one or more symbols using the first encoded bits and bits associated with a second bit level of the multilevel coding scheme. The first binary alphabet polar code is associated with a first coding rate. In addition, the method could include applying a second binary alphabet polar code to a second subset of the multiple bits to generate second encoded bits. The second encoded bits are associated with the second bit level. The second binary alphabet polar code is associated with a second coding rate such that the bit levels have substantially equal error rates.

Abstract: An analog-to-digital converter can produce a digital signal representative of an analog input electrical signal. An optical amplitude modulator can modulate an input optical pulse train using the analog input electrical signal to produce a first modulated optical pulse train. An optical splitter can split the first modulated optical pulse train into a plurality of modulated optical pulse trains. A plurality of detectors can convert the plurality of modulated optical pulse trains into respective modulated voltage pulse trains. A plurality of comparators and a decoder, arranged in a flash converter topology, can receive the modulated voltage pulse trains and output the digital signal representative of the analog input electrical signal using a timing reference derived from the input optical pulse train. Using a relatively high-precision input optical pulse train, such as a Kerr Comb, can produce a relatively high-accuracy analog-to-digital converter.

Abstract: Systems and methods for processing a multitude of variable and varying signals in real time with low latency using fixed hardware with fixed processing resources, such as those within an application-specific integrated circuit (ASIC) or a field-programmable gated array (FPGA). The signal processing systems and methods allow the resource allocation to continuously adjust their processing as a result of changing signal conditions. In accordance with various embodiments, fixed processing resources in ASIC or FPGA form are dynamically allocated through an intelligent interleaving methodology that efficiently maps the signal processing of incoming signals while essentially preserving the same latency as if each signal channel were processed at the full sample rate. This is accomplished by multiplexing under the control of a resource sharing algorithm.

Abstract: A configuration circuit for obtaining a digital code includes a controller circuit that generates a plurality of multibit control words. A digitally controlled current source circuit receives a multibit control word generated by the controller circuit. The digitally controlled current source circuit generates an output current that corresponds to the multibit control word in accordance with a predetermined output curve. A test voltage node receives the output current, and a test voltage develops in response to the output current. A reference voltage node develops a reference voltage, the level of which is independent of the multibit control word. A voltage comparison circuit (i) receives the test voltage and the reference voltage, (ii) compares the two voltages to produce a comparison result and (iii) sends the comparison result to the controller circuit. The digital code is obtained by the configuration circuit using the comparison result and the multibit control word.

Abstract: A connector assembly for an antenna which includes an antenna cover. The connector assembly includes a connector mount with one or more connectors and a connector housing enclosing the connectors. The connector mount extends through an opening in the antenna cover with sufficient clearance to allow movement due to difference in thermal expansion between the antenna cover and the antenna structure. The assembly also includes a flexible seal structure attached to the connector mount and attachable to the antenna cover and dimensioned to enclose a portion of the connector mount extending outside the antenna cover to form a flexible weather resistant seal between the antenna cover and the connector mount while allowing movement of the connector mount relative to the antenna cover.

Abstract: A circuit including an amplifier array including an amplifier stage with M amplifiers (M?2), connected to a resistor interpolator (interpolation order N?2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.

Abstract: Based on received input, a vertex table of the database layer and a vertex key column in the vertex table can be identified. The vertex key column defines vertices of a graph representation. Also based on the received input, an edge table of the database layer, an edge key column in the edge table, a source column in the edge table, and a target column in the edge table can be identified. The source column and target column define relationships between vertices of the plurality of vertices. Within a graph workspace object, graph relationships linking the vertices defined by the vertex key column via edges defined by the source column and target column in the edge table can be assigned, and the graph workspace can be generated in a higher level programming layer based on the graph workspace object.

Abstract: A method and apparatus are disclosed for asynchronous clock generation in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a first logic gate, a second logic gate, a first memory element, a second memory element, and a digital-to-analog converter (DAC). The comparator may initiate an evaluation or precharge operation of comparator inputs. The first logic gate may generate, based on comparator outputs, a first output signal indicating validity of first logic gate output. The second logic gate may generate a second output signal indicating timing reference of bit conversion. The first memory element may generate a third output signal indicating a current state of a bit. The second memory element may generate a plurality of next state bits based on the second output signal and the comparator outputs. The second logic gate may generate the second output signal based on the first and third output signals.

Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.