Patents Examined by Long H. Le
  • Patent number: 10418481
    Abstract: One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has first and second surfaces. A first insulator is formed over a first portion of the channel, and which has a first thickness. A second insulator is formed over the second portion of the channel, and which has a second thickness that is less than the first thickness. A first gate is formed over the first insulator. A second gate is formed over the second insulator. A body region of a second conductivity type is formed above or in the substrate.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 17, 2019
    Assignee: Intersil Americas LLC
    Inventor: Dev Alok Girdhar
  • Patent number: 10378913
    Abstract: A navigation apparatus includes: a current-position information acquisition section obtaining measured current-position information; a camera section obtaining a captured image of a subject; a direction detection section detecting a direction when obtaining the captured image by the camera section; from characteristic-point information related to multiple predetermined characteristic points stored in a storage section, a characteristic-point information extraction section extracting the characteristic-point information related to the characteristic points located in the vicinity of the current position and in a range shown in the direction; and a control section displaying the captured image on a display section, wherein the control section displays a predetermined direction line indicating a distance from the current position on the captured image, obtains a distance and a direction from the current position to the characteristic point, and displays the characteristic-point information at a position correspo
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 13, 2019
    Assignee: Sony Corporation
    Inventor: Hiromasa Miyata
  • Patent number: 10375287
    Abstract: Systems and methods for analyzing scenes from cameras imaging an event, such as a sporting event broadcast, are provided. Systems and methods include detecting and tracking patterns and trails. This may be performed with intra-frame processing and without knowledge of camera parameters. A system for analyzing a scene may include an object characterizer, a foreground detector, an object tracker, a trail updater, and a video annotator. Systems and methods may provide information regarding centers and spans of activity based on object locations and trails, which may be used to control camera field of views such as a camera pose and zoom level. A magnification may be determined for images in a video sequence based on the size of an object in the images. Measurements may be determined from object trails in a video sequence based on an effective magnification of images in the video sequence.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 6, 2019
    Assignee: Disney Enterprises, Inc.
    Inventors: Smadar Gefen, Gregory House, Yuecheng Zhang
  • Patent number: 10373945
    Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 6, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zheng Bian
  • Patent number: 10367055
    Abstract: The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: July 30, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10319638
    Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10304998
    Abstract: A light emitting diode (LED) chip can include: a first pattern region having one or more curved parts; and a second pattern region at least partially surrounding the first pattern region. The first pattern region can include a first conductive type nitride-based semiconductor layer, an active layer, a second conductive type nitride-based semiconductor layer, a top electrode layer, and a top bump layer stacked over a substrate, the second pattern region can include a first conductive type nitride-based semiconductor layer, a bottom electrode layer, and a bottom bump layer stacked over the substrate, and the first pattern region can include one or more protrusion patterns formed in the one or more curved part.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 28, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Chang Hoon Kim, Sang Min Kim, Chi Hyun In, Hong Suk Cho, Dae Seok Park
  • Patent number: 10290702
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Michael A. Stuber, Stuart B. Molin, Jacek Korec, Boyi Yang
  • Patent number: 10290703
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 14, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Jacek Korec, Boyi Yang
  • Patent number: 10283551
    Abstract: A back-illuminated solid-state imaging element includes a semiconductor substrate which has a front surface and a back surface provided with a recess, and in which a thinned section, which is a bottom section of the recess, is an imaging area, a signal read-out circuit formed on the front surface of the semiconductor substrate, a boron layer formed on at least the back surface of the semiconductor substrate and a lateral surface of the recess, a metal layer formed on the boron layer, and provided with an opening opposing a bottom surface of the recess, and an anti-reflection layer formed on the bottom surface of the recess.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 7, 2019
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Masaharu Muramatsu, Hisanori Suzuki, Yasuhito Yoneta, Shinya Otsuka, Hirotaka Takahashi
  • Patent number: 10276520
    Abstract: A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 30, 2019
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Zeng Li, Shou-Yu Hong, Jian-Hong Zeng
  • Patent number: 10269703
    Abstract: A semiconductor device includes: a first conductive line disposed on a substrate, a second conductive line disposed on the substrate, and the second conductive line separated with the first conductive line by a trench; an insulating layer disposed on the first conductive line and the second conductive line, and filled the trench between the first conductive line and the second conductive line; and a magnetic film having a first surface and a second surface opposite to the first surface, and the first surface disposed on the insulating layer; wherein the first surface has a first concave directly above the trench, and the first concave has a first obtuse angle of at least 170 degree.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Yu Ku, Sheng-Pin Yang, Chen-Shien Chen, Hon-Lin Huang, Chien-Chih Chou, Ting-Li Yang
  • Patent number: 10242884
    Abstract: A field-effect transistor and method for fabricating such a field-effect transistor that utilizes an air-sensitive two-dimensional material (e.g., silicene). A film of air-sensitive two-dimensional material is deposited on a crystalized metallic (e.g., Ag) thin film on a substrate (e.g., mica substrate). A capping layer of insulating material (e.g., aluminum oxide) is deposited on the air-sensitive two-dimensional material. The substrate is detached from the metallic thin film/air-sensitive two-dimensional material/insulating material stack structure. The metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is then flipped. The flipped metallic thin film/air-sensitive two-dimensional material/insulating material stack structure is attached to a device substrate followed by having the metallic thin film etched to form contact electrodes. In this manner, the pristine properties of air-sensitive two-dimensional materials are preserved from degradation when exposed to air.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 26, 2019
    Assignees: Board of Regents, The University of Texas System, Consiglio Nazionale delle Ricerche
    Inventors: Deji Akinwande, Li Tao, Carlo Grazianetti, Alessandro Molle
  • Patent number: 10229852
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 10224267
    Abstract: A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching element are fixed on a second substrate. An upper arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. The lower arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 5, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shintaro Araki, Mitsunori Aiko, Takaaki Shirasawa, Khalid Hassan Hussein
  • Patent number: 10177073
    Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
  • Patent number: 10173888
    Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bucknell C. Webb
  • Patent number: 10160634
    Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
    Type: Grant
    Filed: July 16, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bucknell C. Webb
  • Patent number: 10157967
    Abstract: An organic electroluminescence device according to one aspect of the present invention includes: a base material having a top surface on which a recess is provided; a reflective layer provided along at least a surface of the recess; a filling layer filled inside the recess via the reflective layer, the filling layer having light transmissivity; a first electrode provided at least on an upper layer side of the filling layer, the first electrode having light transmissivity; an organic layer provided on an upper layer side of the first electrode, the organic layer including at least a light emitting layer; and a second electrode provided on an upper layer side of the organic layer, the second electrode having light transmissivity, wherein a coloring material is mixed into the filling layer.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 18, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Uchida, Katsuhiro Kikuchi, Satoshi Inoue, Eiji Koike, Masanori Ohara, Yuto Tsukamoto, Yoshiyuki Isomura, Kazuki Matsunaga
  • Patent number: 10157799
    Abstract: A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung