Abstract: A memory device includes a dielectric layer, a bottom electrode, an inter-metal dielectric (IMD) layer, a phase change element in the IMD layer, and a top electrode. The bottom electrode is in the dielectric layer. The IMD layer is over first dielectric layer. The phase change element is in the IMD layer. The top electrode is over the phase change element and is separated from the dielectric layer by at least an air gap free of materials of the IMD layer and the phase change element.

Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: A display panel includes a substrate having an active zone, a pad zone, an external component zone, and a fan-out zone, a plurality of light-emitting elements disposed in the active zone, and a plurality of wire structures. The wire structures include a first wire structure and a second wire structure. The first wire structure includes a plurality of first inner connecting ends, a plurality of first outer connecting ends, and a first body. The second wire structure includes a plurality of second inner connecting ends, a plurality of second outer connecting ends, and a second body. The first wire structure has a first current A1, the second wire structure has a second current A2, and A1>A2. A number of the first inner connecting ends of the first wire structure is N1, a number of the second inner connecting ends of the second wire structure is N2, and N1>N2.

Abstract: A display device includes hole patterns of upper and lower conductive layers that are disposed in a peripheral area of the display device and are asymmetric with respect to an opening of an insulating layer of the display device. A first one of the hole patterns may coincide with a second one of the hole patterns in a part of the peripheral area, while the first one of the hole patterns may cross the second one of the hole patterns in another part of the peripheral area.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

Abstract: An image sensing device to control flow of photocharges using a new method is disclosed. The image sensing device includes a photoelectric conversion region formed in a semiconductor substrate, a floating diffusion (FD) region formed apart from the photoelectric conversion region, a vertical pillar formed between the photoelectric conversion region and the floating diffusion region to transfer the photocharges from the photoelectric conversion region to the floating diffusion (FD) region, and a switching element located between the photoelectric conversion region and the floating diffusion (FD) region.

Abstract: A heat radiation structure includes: a hexagonal boron nitride layer; and a turbostratic structure boron nitride layer provided on a first surface of the hexagonal boron nitride layer.

Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

Abstract: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing an initial base substrate having a middle region and an adjacent edge region; forming a first opening in the middle region of the initial base substrate; forming a first adjustment layer on sidewall surfaces of the first opening; and forming a plurality of second openings with a depth greater than a depth of the first opening in the edge region of the initial base substrate. A portion of the initial base substrate between the first opening and the second opening forms a first fin, a portion of the initial base substrate between adjacent second openings form a second fin. The method also includes forming an isolation structure with a top surface lower than top surfaces of the first fin and the second fins on the surface of the initial base substrate.

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

Abstract: A display device includes a semiconductor member, a first gate electrode, a pixel electrode, and a common electrode. The semiconductor member includes a source area, a drain area, and a channel area between the source area and the drain area. The first gate electrode includes a first gate barrier layer, a second gate barrier layer, and a gate metal layer. The first gate barrier layer overlaps the channel area. An oxide material of the first gate barrier layer is identical to an oxide material of the semiconductor member. The second gate barrier layer includes a metal oxide alloy and is positioned between the first gate barrier layer and the gate metal layer. The pixel electrode is electrically connected to the drain area. The common electrode overlaps the pixel electrode.

Abstract: A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.

Abstract: An anti-reflection bottom-emitting type OLED display device and a manufacturing method are provided. The anti-reflection bottom-emitting type OLED display device includes a substrate, multiple drive transistors, and a light emitting layer. The substrate is provided with a plurality of black matrixes spaced apart from each other. The drive transistors are arranged in an array on the substrate and arranged corresponding to the black matrixes respectively. The light emitting layer is disposed on the drive transistors. An opening region is arranged between each two adjacent black matrixes. The light emitting layer includes multiple light-emitting material layers arranged in an array. Each light-emitting material layer defines a display region and a non-display region. Each opening region is arranged corresponding to each display region, and each non-display region is arranged corresponding to each black matrix. Each display region coincides with each opening region between the black matrixes on the substrate.