Abstract: A blue fluorescent light-emitting layer is provided in common for a subpixel and a subpixel, a green fluorescent light-emitting layer is provided in common for the subpixel and a subpixel, and a red light-emitting layer is provided in common for the subpixel and a subpixel. An opposing surface distance is less than or equal to a Förster radius, and in the subpixel, the green fluorescent light-emitting layer and the red light-emitting layer are layered with a separation layer interposed therebetween.

Abstract: A method for manufacturing a micromechanical component having a disengaged pressure sensor device includes: configuring an electrically conductive sacrificial element in or on a first outer surface of a first substrate; applying a second substrate on or upon the outer surface of the first substrate over the sacrificial element; configuring a pressure sensor device by anodic etching of the second substrate; configuring in the second substrate at least one trench that extends to the sacrificial element; and at least partly removing the sacrificial element in order to disengage the pressure sensor device.

Abstract: Disclosed are a display apparatus and a method for manufacturing the same. The display apparatus comprises: a multi-buffer layer; a pixel array layer formed on the multi-buffer layer and including a plurality of pixels respectively formed as the intersections of a plurality of gate lines and a plurality of data lines; an encapsulation layer formed on the pixel array layer; and an encapsulation substrate formed on the encapsulation layer and including a display area and a non-display area adjacent to the display area, wherein, the encapsulation substrate is for supporting the display area and the non-display area such that there is no base substrate in the display apparatus.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.

Abstract: An epitaxial substrate for semiconductor elements suppresses leakage current and has a high breakdown voltage. The epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer formed of a group 13 nitride adjacent to the free-standing substrate; a channel layer formed of a group 13 nitride adjacent to the buffer layer; and a barrier layer formed of a group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing Si at a concentration of 1×1017cm?3 or more, and a minimum value of a concentration of Zn in the second region is 1×1017cm?3.

Abstract: A manufacturing method of a flexible OLED panel, a flexible OLED panel, and a display is disclosed. The flexible OLED panel is manufactured by the manufacturing method, and the display includes the flexible OLED panel. The disclosure functions as a role of blocking crack diffusion by forming the opening holes in the inorganic layer to release the cracking stress; the opening holes are arranged in at least two rows, and two of the rows of the opening holes adjacent to each other are arranged in a dislocation manner in the surrounding direction so as to distribute at least one of the opening holes on a line connecting any position on the boundary of the second area away from the first area to any position of the display area, the diffusion of cracks at any position in the inorganic layer can be blocked by at least one of the opening holes.

Abstract: A display panel includes a substrate including a circuit layer, an insulation layer on the substrate, the insulation layer defining a hole, a first electrode on the insulation layer, the first electrode being electrically connected to the circuit layer in the hole, a light absorbing layer on the first electrode and overlapping the hole, a pixel defining layer on the insulation layer and defining an opening through which a top surface of the first electrode is exposed, at least one organic layer including a light emitting layer in the opening, and a second electrode on the at least one organic layer.

Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.

Abstract: A layered apparatus comprises a substrate (100), a first electrically conductive layer (102) on and in contact with the substrate (100), a second patterned electrically conductive layer (104) which is in contact with the first electrically conductive layer (102), a third electrically conductive layer (112), a fourth electrically conductive layer (114) which is electrically insulated from the first electrically conductive layer (102), the second patterned electrically conductive layer (104) and the third electrically conductive layer (112), and an operationally active layer (108) between the first electrically conductive layer (102) and the fourth electrically conductive layer (114). The second patterned electrically conductive layer (104) is thicker than the operationally active layer (108), and a top part (104A) of the second patterned electrically conductive layer (104) extends across the operationally active layer (108) for having an electrical contact with the third electrically conductive layer (112).

Abstract: A method of manufacturing a light emitting element includes: providing a wafer comprising: a sapphire substrate having a first face and a second face, and a semiconductor structure disposed on the second face; irradiating the substrate with a laser beam to form a plurality of modified regions in the substrate; and subsequently, separating the wafer into a plurality of light emitting elements.

Abstract: An imaging device includes a semiconductor substrate that includes a pixel region where pixels are arranged and a peripheral region adjacent to the pixel region; an insulating layer that covers the pixel region and the peripheral region; a first electrode that is located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrode; a second electrode that covers the photoelectric conversion layer; and a first layer that covers the second electrode, the first layer being located above the pixel region and the peripheral region. A thickness of the first layer above the peripheral region is larger than a thickness of the first layer above the pixel region. A level of an uppermost surface of the first layer above the peripheral region is higher than a level of an uppermost surface of the first layer above the pixel region.

Abstract: An automatic master slave system and approach for coordinated control of a parameter, for example, a heating, ventilation and air conditioning condition, in an area of multiple spaces controlled by room controllers. Changing a layout of a zone/area in a building such as moving, adding or removing a door, increasing or splitting size of a room through movable walls, or by permanently removing partitions, changing offices to a conference room or vice versa, may occur. A size of a room may be altered within minutes, according to customer demand. For instance, rooms may be converted into a single room by removing partitions. The controllers that were controlling temperatures of the rooms independently earlier, may convert automatically into a master-slave configuration and now work together to control a larger room. If the large room is split into multiple rooms, the controllers may automatically revert to their previous configuration.

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: An integrated electronic device forming a power device and including: a semiconductor body; a first conductive region and a second conductive region, which extend over the semiconductor body, the second conductive region surrounding the first conductive region at a distance; and an edge termination structure, which is arranged between the first and second conductive regions and includes a dielectric region, which delimits an active area of the power device, and a semiconductive structure, which extends over the dielectric region and includes a plurality of diode chains, each diode chain including a plurality of first semiconductive regions of a first conductivity type and a plurality of second semiconductive regions of a second conductivity type, the first and second semiconductive regions being arranged in alternating fashion so as to form a series circuit including a plurality of first and second diodes, which are spaced apart from one another and have opposite orientations.

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

Abstract: Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a plurality of signal lines formed in the display area; a pad formed in the peripheral area; and a plurality of connection wires for connecting the signal lines and the pad, wherein a first connection wire and a second connection wire neighboring the first connection wire from among the plurality of connection wires are disposed on different layers, and the first connection wire and the second connection wire, which are formed to extend from the pad and are bent at least twice to have at least one being bent toward backward direction, are disposed in the peripheral area.