Patents Examined by Long Pham
  • Patent number: 10679945
    Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 9, 2020
    Assignee: INTELLECTUAL VENTURES HOLDING 81 LLC
    Inventors: Robert P. Masleid, James B. Burr, Michael Pelham
  • Patent number: 10672654
    Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 2, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 10672706
    Abstract: A semiconductor device includes a multilayer wiring structure on a substrate. The multilayer wiring structure includes: a top wiring; a fuse element, which is located on a lower layer-side of the top wiring, and is made of metal having a melting point that is higher than that of the top wiring; and a lower-layer wiring, which is connected to each of ends of the fuse element. Provided is a semiconductor device in which fuse elements made of the high-melting point metal are arranged at high density.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: ABLIC INC.
    Inventor: Yoshitaka Kimura
  • Patent number: 10658370
    Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Kuan-Lun Cheng, Yasutoshi Okuno, Jiun-Jia Huang
  • Patent number: 10658455
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yin Hsu, Chun Li Wu, Ching-Hung Kao
  • Patent number: 10658202
    Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: May 19, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10651141
    Abstract: The disclosure relates to the field of display technologies and particularly to a chip, a flexible display panel and a display device. The chip includes a body and a plurality of connection terminals arranged on a surface of the body, where each connection terminal is provided with a stress concentration resisting structure for preventing from producing the stress concentration phenomenon.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 12, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Liqiang Chen, Paoming Tsai, Jianwei Li, Chen Xu
  • Patent number: 10636742
    Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 28, 2020
    Assignee: Dialog Semiconductor (US) Limited
    Inventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
  • Patent number: 10636722
    Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
  • Patent number: 10636697
    Abstract: A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 10629767
    Abstract: An integrated circuit includes a substrate material that includes an epitaxial layer, wherein the substrate material and the epitaxial layer form a first semiconductor material with the epitaxial layer having a first conductivity type. At least one nanowire comprising a second semiconductor material having a second conductivity type doped differently than the first conductivity type of the first semiconductor material forms a junction crossing region with the first semiconductor material. The nanowire and the first semiconductor material form an avalanche photodiode (APD) in the junction crossing region to enable single photon detection. In an alternative configuration, the APD is formed as a p-i-n crossing region where n represents an n-type material, i represents an intrinsic layer, and p represents a p-type material.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 21, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Narsingh B. Singh, John V. Veliadis, Bettina Nechay, Andre Berghmans, David J. Knuteson, David Kahler, Brian Wagner, Marc Sherwin
  • Patent number: 10629524
    Abstract: A memory and a method for fabricating the memory are provided. The memory includes a bit-line layer on a semiconductor substrate and having bit lines arranged in the bit-line layer. The memory also includes a shielding layer on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. Further, the memory includes a word-line layer on the shielding layer and having word lines arranged in the word-line layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 21, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Peng Huang, Xue Hai Zhang, Chuan Miao Zhou
  • Patent number: 10622208
    Abstract: A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalls from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalls. The lateral semiconductor nanotube shell comprises a hexagonal shape.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Peng Xu, Choonghyun Lee
  • Patent number: 10622218
    Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Michael Roesner, Georg Ehrentraut
  • Patent number: 10622379
    Abstract: A semiconductor structure is provided that includes a plurality of high mobility semiconductor material (i.e., silicon germanium alloy of III-V compound semiconductors) fins located above and spaced apart from a bulk semiconductor substrate portion, wherein each of the high mobility semiconductor material fins has a lower faceted surface that is confined within a dielectric isolation structure.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10622302
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Patent number: 10622402
    Abstract: A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring, an insulating layer, and a second wiring that is electrically connected to the first wiring in an opening of the insulating layer. The insulating layer has a first curved portion that covers an inner surface of a through hole between a first opening and a second opening and a second curved portion that covers an edge of the second opening. A surface in the first curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole. The surface in the second curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 14, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Noburo Hosokawa, Nao Inoue, Katsumi Shibayama
  • Patent number: 10615274
    Abstract: A vertical semiconductor device includes a substrate, a buffer layer over the substrate, and a drift layer over the buffer layer. The substrate has a first doping type and a first doping concentration. The buffer layer has the first doping type and a second doping concentration that is less than the first doping concentration. The drift layer has the first doping type and a third doping concentration that is less than the second doping concentration.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Cree, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt
  • Patent number: 10615219
    Abstract: A method for fabricating an optical sensor includes: forming, over a substrate, a first material layer comprising a first alloy of germanium and silicon having a first germanium composition; forming, over the first material layer, a graded material layer comprising germanium and silicon; and forming, over the graded material layer, a second material layer comprising a second alloy of germanium and silicon having a second germanium composition. The first germanium composition is lower than the second germanium composition and a germanium composition of the graded material layer is between the first germanium composition and the second germanium composition and varies along a direction perpendicular to the substrate.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 7, 2020
    Assignee: ARTILUX, INC.
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen
  • Patent number: 10607935
    Abstract: A memory device comprises electrode layers stacked in a stacking direction. Semiconductor pillars penetrate the electrode layers in the stacking direction. First wirings are disposed above the plurality of electrode layers at a first level. Each first wiring is electrically connected to a semiconductor pillar. A second wiring is disposed above the plurality of electrode layers at the first level. The second wiring is insulated from semiconductor pillars. The second wiring and the first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction. A width of the second wiring the second direction is equal to a width of each first wiring. A spacing distance between the second wiring and a nearest first wiring is greater than a spacing interval between adjacent first wirings.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hideto Takekida