Patents Examined by Long Pham
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10529917
    Abstract: A magnetic tunneling junction (MTJ) with a free layer that is less temperature sensitive and is reflow compatible at 260° C. The magnetic free layer may include various configurations, such as a single as-deposited crystalline magnetic layer or a composite free layer with more than one magnetic layers or a combination of composite and single magnetic layers. The layers of the composite magnetic free layer may include as-deposited crystalline magnetic free layers or a combination of as-deposited crystalline and as-deposited amorphous magnetic layers, with or without a spacer layer. An interface layer may be provided at an interface between the free layer and adjacent layer to apply tensile stress on the free layer in the direction perpendicular to the in-plane direction to enhance perpendicular magnetic anisotropy (PMA) of the free layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Kazutaka Yamane, Seungmo Noh, Kangho Lee, Vinayak Bharat Naik
  • Patent number: 10522551
    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
  • Patent number: 10515888
    Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Pin-Tso Lin, Chia-Hsin Chen
  • Patent number: 10515906
    Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Patent number: 10510704
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 10510646
    Abstract: A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10504750
    Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 10, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10497690
    Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10497656
    Abstract: A packaged radio-frequency device is disclosed, including a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The packaging substrate may include a first component mounted on the first side of the packaging substrate and a first overmold structure implemented on the first side of the packaging substrate, the first overmold structure substantially encapsulating the first component. The packaging substrate may further include a set of through-mold connections implemented on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins, a second component mounted on the second side of the packaging substrate, the second component being located in an area of the second side configured to implement redundant ground pins and a second overmold structure substantially encapsulating one or more of the second component or the set of through-mold connections.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 3, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Robert Francis Darveaux, Anthony James Lobianco
  • Patent number: 10490689
    Abstract: Methods of hydrogen atom incorporation and of passivation of grain boundaries of polycrystalline semiconductors use a low temperature, pulsed plasma to incorporate hydrogen atoms into the grain boundaries of polycrystalline semiconductor materials in a controlled manner. A hydrogen-passivated polycrystalline IR detector has hydrogen atoms incorporated into grain boundaries of a polycrystalline Group III-V compound semiconductor detector element and a dark current density characteristic that is lower than the dark current density characteristic of a polycrystalline IR detector without the incorporated hydrogen atoms.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 26, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Sevag Terterian, Terence J. DeLyon, Bor-An Clayton Tu, Hasan Sharifi
  • Patent number: 10483360
    Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 10483153
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Patent number: 10483128
    Abstract: Epitaxial wafers with a high concentration of BMD nuclei or developed BMDs just below a denuded zone, and having low surface roughness, are produced by forming an oxynitride layer on a purposefully oxidized epitaxial layer by a short RTA treatment in a nitriding atmosphere, removing the oxynitride layer, and then polishing the epitaxial surface.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 19, 2019
    Assignee: SILTRONIC AG
    Inventors: Timo Mueller, Michael Gehmlich, Frank Faller
  • Patent number: 10475790
    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Barn Chen, Chi-Cherng Jeng, Shiu-Ko Jangjian, Ting-Huang Kuo
  • Patent number: 10475779
    Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 12, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Seung Wook Yoon
  • Patent number: 10475724
    Abstract: A heat exchanger for cooling a plurality of heat-generating components with flat surfaces arranged in spaced parallel relation to one another has at least three flat, fluid-carrying panels, including a first end panel, a second end panel, and at least one middle panel. The middle panels have both of their opposed surfaces in thermal contact with a surface of a heat generating component. The end panels each have one surface in thermal contact with a surface of a heat-generating component. Inlet and outlet manifolds of the heat exchanger are in communication with the inlet and outlet openings of the middle panels. The inlet manifold communicates with the inlet opening of the first end panel, the outlet manifold communicates with the outlet opening of the second end panel, and the outlet opening of the first end panel communicates with the inlet opening of the second end panel.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 12, 2019
    Assignee: Dana Canada Corporation
    Inventors: Meinrad K. A. Machler, Colin A. Shore
  • Patent number: 10475770
    Abstract: Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 12, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Won Geol Lee, Won Chul Do, Ji Hun Yi
  • Patent number: 10475956
    Abstract: An optoelectronic device comprising a semiconductor structure includes a p-type active region and an n-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell comprises at least two distinct substantially single crystal layers.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 12, 2019
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 10475736
    Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Arnab Sarkar, Arghya Sain, Kristof Darmawikarta, Henning Braunisch, Prashant D. Parmar, Sujit Sharan, Johanna M. Swan, Feras Eid