Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.

Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

Abstract: A multilayer coil component includes a multilayer body formed by stacking a plurality of insulating layers and including a coil built in the multilayer body, and first and second outer electrodes electrically connected to the coil. The coil is formed by electrically connecting a plurality of coil conductors stacked together with the insulating layers. The multilayer coil component further includes, inside the multilayer body, first and second connecting conductors. The first connecting conductor connects between a portion of the first outer electrode covering the first end face, and a coil conductor facing the portion. The second connecting conductor connects between a portion of the second outer electrode covering the second end face, and a coil conductor facing the portion. The multilayer coil component has a transmission coefficient S21 at 40 GHz of from about ?1.0 dB to about 0 dB.

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

Abstract: Light trapping pixels, devices incorporating such pixels, and various associated methods are provided. In one aspect, for example, a light trapping pixel device can include a light sensitive pixel having a light incident surface, a backside surface opposite the light incident surface, and a peripheral sidewall disposed into at least a portion of the pixel and extending at least substantially around the pixel periphery. The pixel can also include a backside light trapping material substantially covering the backside surface and a peripheral light trapping material substantially covering the peripheral sidewall. The light contacting the backside light trapping material or the peripheral light trapping material is thus reflected back toward the pixel.

Abstract: Provided is a double-side polishing apparatus and a double-side polishing method which make it possible to terminate double-side polishing with timing allowing a work having been polished to have a target shape. A computing unit 13 performs a step of grouping the data of thicknesses measured using work thickness measuring devices 11 on a work basis; a step of extracting shape components of each work from the thickness data; a step of identifying a position of each of the shape components in the work radial direction; a step of computing a shape distribution of the work from the identified position ; a step of obtaining a shape index of the work from the computed shape distribution; and a step of determining timing of termination of the double-side polishing based on the obtained shape index, thus timing of termination of the double-side polishing is determined.

Abstract: A semiconductor package includes an interposer including first and second surfaces opposite to each other. The semiconductor package also includes a heat dissipation layer disposed on the first surface of the interposer and a first semiconductor die mounted on the first surface of the interposer. The semiconductor package additionally includes a stack of second semiconductor dies mounted on the second surface of the interposer. The semiconductor package further includes a thermally conductive connection part for transferring heat from the stack of the second semiconductor dies to the heat dissipation layer.

Abstract: Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.

Abstract: Embodiments relate to a die package featuring a sputtered metal shield to reduce Electro-Magnetic Interference (EMI). According to a particular embodiment, a die featuring a top surface exposed by surrounding Molded Underfill (MUF) material, is subjected to metal sputtering. The resulting sputtered metal shield is in direct physical and thermal contact with the die, and is in electrical contact with a substrate supporting the die (e.g., to provide shield grounding). Specific embodiments may be particularly suited to reducing the EMI of a package containing an electro-optic die, to between 3-15 dB. The conformal nature and small thickness of the sputtered metal shield desirably conserves space and reduces package footprint. Direct physical contact between the shield and the die surface exposed by the MUF, enhances thermal communication (e.g., reducing junction temperature). According to certain embodiments, the sputtered metal shield comprises a stainless steel liner, copper, and a stainless steel coating.

Abstract: A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

Abstract: A method and a system for planarizing a membrane is disclosed. In one aspect, the method includes providing a resilient membrane and planarizing the surface of the membrane with a conditioning tool. The planarized membrane may be used in chemical mechanical planarization of a wafer. The method further includes finishing the surface of a wafer with the planarized membrane.

Abstract: A conductive member module has a pair of conductive members formed in a plate shape and facing each other, and a sealing part. The conductive member module is produced by performing an accommodation step, a sealing step, and an extraction step. In the accommodation step, the two individual conductive members are sandwiched in the facing orientation thereof by outer support members abutting outer surfaces of the conductive members, and inner support members abutting inner surfaces of the conductive members. Outer recesses are formed in the outer surfaces by the outer support members, and inner recesses are formed in the inner surfaces by the inner support members. The outer recesses are deeper in the Z direction than the inner recesses.

Abstract: A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole.

Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.

Abstract: The present disclosure relates to a solid-state imaging device capable of further decreasing reflectivity, a method of manufacturing the same, and an electronic device. The solid-state imaging device includes a semiconductor substrate on which a photoelectric converting unit is formed for each of a plurality of pixels, and an antireflection structure provided on a light incident surface side from which light is incident on the semiconductor substrate in which a plurality of types of projections of different heights is formed. The antireflection structure is formed by performing processing of digging a light incident surface of the semiconductor substrate in a plurality of stages with different processing conditions. The antireflection structure is the structure in which a second projection lower than a first projection is formed between the first projections of predetermined height. The present technology may be applied to a CMOS image sensor, for example.

Abstract: A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

Abstract: An electronic package is provided, including at least an electronic element and at least an antenna structure disposed on a carrier structure. The antenna structure includes a base portion configured with an antenna body and a plurality of support portions disposed on the base portion. As such, the base portion is disposed over the carrier structure through the support portions and a plurality of open areas are formed between the base portion and the carrier structure to serve as an air gap, thereby effectively improving the performance gain and efficiency of the antenna body.

Abstract: The present disclosure is directed to a polishing head for polishing a wafer by a slurry. The polishing head includes a main body and at least two air modules. The main body has a cavity for accommodating the wafer, a main channel, and at least two sub-channels connected to the main channel. The at least two air modules are disposed at an outer surface of the main body. Each of the air modules is respectively connected to one of the sub-channels of the main body and configured to generate an air stream. When the polishing head rotates, the air stream forms an air curtain around the outer surface of the main body.

Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.