Patents Examined by Long Pham
  • Patent number: 10475922
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 12, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10468367
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
  • Patent number: 10461023
    Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
  • Patent number: 10461035
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Patent number: 10461168
    Abstract: A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric formed between an elevated source and an elevated drain and surrounding a metal gate, and performing a chemical mechanical planarization (CMP) process on an upper surface of the elevated source, and in which a height of the metal gate becomes lower than a height of the elevated source according to the CMP process.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwan Jae Song
  • Patent number: 10453738
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 22, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 10455717
    Abstract: The present invention discloses a modularized circuit for isolated circuit, wherein the isolated circuit includes at least two circuit components connecting in parallel and/or series, the circuit components, according to a circuit connection configuration, weld corresponding pins of the components directly, forming an integrated module in accordance with a desired connection method of the circuit, and saving circuit boards and wires; the circuit components are designed as a parallelepiped, and a plurality of bonding pads are arranged on part of an area on a surface of the parallelepiped. Due to constructing a circuit unit by welding connections in a way of building blocks, welding directly between components in a 3D space, comparing to the circuits limited in a circuit board plane as a PCB, it owns a wider design space.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: October 22, 2019
    Assignee: SHENZHEN XILONG TOY COMPANY LIMITED
    Inventor: Yipu Zheng
  • Patent number: 10446599
    Abstract: An image sensor includes a pixel array having a plurality of pixels arranged therein. At least any one of the plurality of pixels include: a photoelectric conversion unit including first and second photoelectric conversion elements; a first sub-lens formed over the first photoelectric conversion element, and having a vertex out of a central axis of the first photoelectric conversion element; a second sub-lens formed over the second photoelectric conversion element, and having a vertex out of a central axis of the second photoelectric conversion element; and a microlens formed over the photoelectric conversion element so as to overlap the first and second sub-lenses. The first sub-lens is symmetrical with the second sub-lens, based on a boundary surface between the first and second photoelectric conversion elements.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Minsu Cho
  • Patent number: 10438936
    Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 8, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Osvaldo Jorge Lopez, Walter Hans Paul Schroen, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Patent number: 10431739
    Abstract: Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Rigano, Fabio Pellizzer
  • Patent number: 10431617
    Abstract: There is provided a photoelectric conversion device in which a distance from a main surface to an inner surface of a first part of a dielectric film is smaller than a distance from the main surface to a top surface of a light shielding member, a distance from the main surface to an outer surface of the first part is smaller than a distance from the main surface to an outer surface of a second part of the dielectric film, an outer surface of a third part inclines to the top surface, a surface of a dielectric member inclines to the top surface, between the dielectric film and the top surface in a normal direction, and the dielectric member has a refractive index lower than a refractive index of the dielectric film.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akihiro Kawano, Yoshiyuki Nakagawa, Masao Ishioka, Takashi Okagawa
  • Patent number: 10424590
    Abstract: There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. The method may include forming a plurality of vertical holes by etching a portion of the stack structure. The method may include forming a memory layer and a channel layer along internal surfaces of the vertical holes. The method may include forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes. The method may include exposing a portion of the channel layer and the first conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer. The method may include forming another conductive layer along surfaces of the exposed portion of the channel layer and the first conductive layer.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10424660
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 10418488
    Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Pierre Morin
  • Patent number: 10410930
    Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Patent number: 10411114
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin, with a top surface of the insulator material in contact with a bottom surface of the first spacer layer. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu, Peng Xu
  • Patent number: 10411036
    Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 10410941
    Abstract: A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Nexperia B.V.
    Inventors: Chi Ho Leung, Pompeo V. Umali, Shun Tik Yeung, Kan Wae Lam
  • Patent number: 10403717
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
  • Patent number: 10403618
    Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chandra S. Tiwari, Tony M. Lindenberg, Jonathan S. Hacker, Christopher J. Gambee, Kurt J. Bossart