Abstract: A recursive digital filter and method for filtering an n-bit digital input signal. The filter includes a summing circuit which receives an input signal. A second summing circuit is also provided which is coupled to the first summing circuit. Further provided is a feedback circuit which is operable to allow the first and second summing circuits to generate a filtered output signal without using a multiplier.

Abstract: A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.

Abstract: In a prehcarge-type carry chained adder circuit, stages as represented by adders are grouped into a plurality of blocks each consisting of a plurality of stages. When the propagating functions of the stages of each block are active, a carry signal reproduced from the preceding block is transferred to the succeeding blocks through a bypass circuit.

Abstract: A keyboard apparatus comprises a row of control keys operated by the left-hand thumb of an operator, a row of control keys operated by the operator's right-hand thumb, a first group of data entry keys arranged in a matrix of three rows and five columns in a first working area to be operated by the operator's first to fourth left-hand fingers, and a second group of data entry keys arranged in the same manner as the first in a second working area to be operated by the operator's first to fourth right-hand fingers. The first and second working areas are oriented so that the columns of the first and second groups are generally aligned with the left- and right-hand fingers, respectively.

Abstract: A data compare circuit includes an inverter (I1), a first group (20) of series-connected transistors, a second group (20) of series-connected transistors, and a switching device (24). The switching device (24) causes a common equal line (18) to be discharged from a precharged high voltage level to a low logic level when an equality does not exist.

Abstract: A circuit for the fast calculation of the discrete cosine transform (X.sub.i), 0.ltoreq.i.ltoreq.N-1, in which N=2.sup.n and n is an integer of a signal defined by a sequence (x.sub.i), 0.ltoreq.i.ltoreq.N-1 includes a first adder stage receiving the sequence (x.sub.i), 0.ltoreq.i.ltoreq.N-1, and supplying two sequences (x.sub.i.sup.o) and y.sub.i.sup.i) and 0.ltoreq.i.ltoreq.(N/2)-1, a group of upper half-stages receiving the sequence of x.sup.o.sub.i) and supplying the sequence (X.sub.2q) of the even components of the cosine transform. That group constitutes a circuit for the fast calculation of the cosine transform for a group of (N/2) points and a group of lower half-stages receiving the sequence (y.sub.i) and supplying the sequence (X.sub.2q+1) of the odd components of the cosine transform.

Abstract: A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.

Abstract: An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.

Abstract: A miniaturized single-hand keyboard for computers or electronic word processing systems comprising alphabetical, numerical, and programmable keys. The keyboard is used in conjunction with a keypointer which presses any of the keys on the keyboard. The keypointer has a number of keys such as a shift key, control key and an alternate key, which are activated by pressure of the thumb or the index finger.

Abstract: An apparatus and method for determining remaining distance to the green and for selecting an appropriate club to use in advancing the golf ball over the remaining distance. A device for storing the distances achieved in the past with a selected club is operated to yield a statistical value useful in selecting the club to use on the next stroke. In addition, the method and apparatus measures directly the distance achieved with the club used to advance the golf ball toward the green, and performance information is continually updated to provide currently-accurate performance information upon which to base the selection about which club to use on the next stroke.

Abstract: A wave shaping circuit includes a digital sampling circuit for sampling an input signal and producing a digital signal. The sampled signal is detected by a sign detector for detecting whether it is positive or negative. A unit difference generator is provided for generating a unit difference which is equal to a difference increased, during one sampling cycle, in a positive or negative direction as detected by the sign detector. A register is provided for storing a summed difference obtained in the previous sampling cycle. The summed difference is multiplied by a predetermined coefficient which is between 0 and 1 so that the product changes exponentially. A first adder is provided for adding the summed difference multiplied by the coefficient with the unit difference. The added result is stored in the register. A second adder is provided for adding the sampled input signal with the summed signal stored in the register, and producing a corrected signal.

Abstract: In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.

Abstract: A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.

Abstract: Real-time all-optical multiplication of an n component vector by a large m by m matrix having digital accuracy utilizes an updatable two dimensional spatial light modulator.

Abstract: A digital filter processor employs four multiplier-accumulator cells and an output accumulator for receiving and accumulating all cell outputs. Data is provided to all cells in parallel, and finite impulse coefficients are applied serially to all cells. A plurality of registers and at least one multiplexer interconnect the cells for transmitting the coefficients between cells. The registers can be employed for sample rate reduction or decimation. A plurality of processors can be cascaded for processing an increased number of coefficients without a reduction in sample time. Alternatively, data can be recycled in a processor to accommodate a number of coefficients greater than the number of cells at a reduced sampled sample rate. A cell address is provided for selecting cell outputs during the reading of the filtered/processed data.

Abstract: A bit-serial pipeline Galois Field multiplier for multiplying an element K(X)=K.sub.m-1 X.sup.m-1 +K.sub.m-2 X.sup.m-2 X.sup.m-2 +. . . +K.sub.0 with another element Y(X)=Y.sub.m-1 X.sup.m-1 +Y.sub.m-2 X.sup.m-2 +. . . +Y.sub.0 to obtain Z.sub.0 =Z.sub.m-1 X.sup.m-1 +Z.sub.m-2 X.sup.m-2 +. . . +Z.sub.0, which is also an element of the field generally defined by P(X)=a.sub.m X.sup.m +a.sub.m-1 X.sup.m-1 +a.sub.m-2 X.sup.m-2 +. . . a.sub.1 X+a.sub.0. The multiplier has an input shift register buffer circuit, an intermediate shift register circuit, an output shift register circuit and multiplying and summing device. The input shift register buffer circuit is configured for serially receiving the K(X) coefficients. The multiplying and summing device receives arrangements of K(X) coefficients and the Y(X) coefficients and operates thereon, by multiplying corresponding pairs of register stage elements and Y(X) coefficients and summing the products.

Abstract: A programmable calculator using at least one exchangeable reloadable memory module includes a connector for connecting the exchangeable reloadable memory module to the calculator. The calculator judges whether a program including information to execute said program is present in said exchangeable reloadable memory module, and inhibits erasure of the information to execute the program when presence of the program in the exchangeable reloadable memory module is judged by the calculator at the time of initialization of the programmable calculator.

Abstract: A monolithic high performance processor for computing digital signal processing algorithms based on the Fast Fourier Transform. The monolithic processor employs an array of bit-serial multipliers which cooperate with bit-serial adder/substractors to produce fast results with great precision, with reduced printed-circuit board space, and with low power requirements. The processor uses local asynchronous control and simple interfacing with the host computer. The processor, which is applicable to a broad spectrum of digital signal processing, including digital audio, radar/sonar, seismic and speech processing, operates in a variety of modes which allow the device to perform Fast Fourier Transforms, Inverse Fast Fourier Transforms, windowing, multiplication, Finite Impulse Response filtering, convolution and correlation.

Abstract: A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

Abstract: An auto-correlation apparatus for producing N auto-correlation values R(k), (k=0, . . . N-1) of an auto-correlation function of a sequence of digital samples x(n), (n=-.infin. . . . 0, . . . p) of an input signal, each sample being encoded as words of "b" binary bits, each value R(k) being defined by the formula: ##EQU1## wherein M is the number of digital samples. The apparatus comprises a random access memory for storing at respective addresses therein words (X,R) each of which is a concatenation of a word representing the value of a signal sample (X) and a word representing an auto-correlation value (R). A multiplier cooperating with an adder performs multiplying and summing operations on the M most recent signal sample words in accordance with the formula for R(k). A memory addressing and sequencing member supplies an addressing cycle to the memory for each received signal sample words, and controls the operations of the multiplier and adder.