Patents Examined by M. Wilczewski
  • Patent number: 7666750
    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: February 23, 2010
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Daniel C. Kerr, Nace M. Rossi
  • Patent number: 7666779
    Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: February 23, 2010
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Patent number: 7666766
    Abstract: The present invention relates to a film formation apparatus including a first transfer chamber having a roller for sending a substrate, a film formation chamber having a discharging electrode, a buffer chamber provided between the transfer chamber and the film formation chamber or between the film formation chambers, a slit provided in a portion where the substrate comes in and out in the buffer chamber, and a second transfer chamber having a roller for rewinding the substrate. The slit is provided with at least one touch roller, and the touch roller is in contact with a film formation surface of the substrate. In addition, the present invention also relates to a method for forming a film and a method for manufacturing a photoelectric conversion device that are performed by using such a film formation apparatus.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: February 23, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshikazu Hiura, Hiroki Adachi, Hironobu Takahashi, Yuusuke Sugawara, Tatsuya Arao, Kazuo Nishi, Yasuyuki Arai
  • Patent number: 7666797
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 7666767
    Abstract: A mask for sequential lateral solidification (SLS) process with at least one transparency region is provided. The transparent region is defined by two lengthwise edges, a front edge, and a rear edge. The two lengthwise edges also define a quadrilateral. The front edge is located outside the quadrilateral, and the rear edge is located inside the quadrilateral.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: February 23, 2010
    Assignee: AU Optronics Corp.
    Inventor: Ming-Wei Sun
  • Patent number: 7666764
    Abstract: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group IVA elements, group VA elements, group VIA elements, and transitional metals. The method for forming an active layer of a thin film transistor device by using the compound semiconductor material of the present invention is disclosed therewith.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Jia-Chong Ho, Jen-Hao Lee, Cheng-Chung Lee, Yu-Wu Wang, Chun-Tao Lee, Pzng Lin
  • Patent number: 7663225
    Abstract: In a manufacturing process of electronic components which include conductive patterns laminated with insulating layers provided therebetween, conductive pattern layers having conductive patterns formed at intervals therebetween along layer surfaces and insulating layers are alternately laminated to each other. The laminate is pressed by applying a force thereto in the lamination direction, followed by cutting of the laminate along cutting lines provided along boundaries between the electronic components, so that the electronic components are separated from each other. In a cutting-removal region of a mother substrate from which the electronic components are separated from each other by cutting, removal dummy patterns having a size allowing it to be disposed within the above region are formed. In the electronic component, floating dummy patterns which are not electrically connected to the conductive patterns are formed at intervals from the cutting-removal region.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: February 16, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuhide Kudo, Minoru Matsunaga
  • Patent number: 7663236
    Abstract: Disclosed herein is a semiconductor electrode with improved power conversion efficiency through inhibition of recombination reactions of electrons. The semiconductor electrode comprises a transparent electrode consisting of a substrate and a conductive material coated on the substrate, and a metal oxide layer formed on the transparent electrode wherein the metal oxide layer contains a phosphate. Further disclosed is a solar cell employing the semiconductor electrode.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Sung Lee, Young Jun Park, Sang Cheol Park, Jung Gyu Nam, Ju Chul Park
  • Patent number: 7659148
    Abstract: A bonding method and an apparatus that enable metal bonding under the atmospheric pressure and at room temperature, wherein the surfaces of objects (1b, 2a) to be bonded together are cleaned in an initial cleaning step (S1) to remove bonding inhibitor substances (G) such as oxides and adhered substances; one (1b) of the bonding surfaces is provided with an uneven profile with a predetermined roughness in a surface roughness control step (S3); a surface treatment step (S5) is performed to remove the substances (F) that have been removed but adhered to the bonding surfaces (1b, 2a) again; and the uneven bonding surface (1b) is pressed against the other bonding surface (2a) to bond them together.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: February 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Tatsuo Sasaoka, Satoshi Horie, Isamu Aokura, Yoshihiko Yagi, Kazuki Fukada
  • Patent number: 7659206
    Abstract: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer of silicon oxide. The silicon oxide is removed by exposure to a plasma of fluorine-containing process gas. Alternatively, the remaining silicon oxide can be removed by a fluorine-containing acidic bath. In yet another version, a plasma of a fluorine-containing gas and an oxygen-containing gas is energized to remove the silicon oxycarbide from the substrate.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Krishna Vepa, Yashraj Bhatnagar, Ronald Rayandayan, Venkata Balagani
  • Patent number: 7655517
    Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, George I. Bourianoff
  • Patent number: 7651944
    Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: January 26, 2010
    Assignee: Nanosys, Inc.
    Inventors: Xiangfeng Duan, R. Hugh Daniels, Chunming Niu, Vijendra Sahi, James M. Hamilton, Linda T. Romano
  • Patent number: 7652298
    Abstract: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the structure thus obtained into individual flip chip type LED lighting devices.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: January 26, 2010
    Assignee: Neobulb Technologies, Inc.
    Inventors: Jeffrey Chen, Chung Zen Lin
  • Patent number: 7646011
    Abstract: An organic light emitting display device is disclosed. The device includes a substrate; a first electrode formed on the substrate; an organic layer including at least an emission layer and formed on the first electrode; and a second electrode formed on the organic layer. The emission layer includes a host and a dopant material. The dopant is one of materials having the structure of Formula 1, where R may be one selected from the group consisting of ethylene, an ethylene derivative, stilbene, a stilbene derivative. Also, R1 to R6 may be different from or equal to each other, and each is selected from the group consisting of a hydrogen atom, a halogen atom, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C5 to C20 aryl group, a C3 to C30 heterocyclic group, and an aliphatic C3 to C30 hydrocarbon group.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: January 12, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jun-Yeob Lee, Min-Seung Chun, Yong-Joong Choi
  • Patent number: 7646014
    Abstract: Disclosed is an organic thin film transistor, including a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, and source/drain electrodes, in which a fluorine-based polymer thin film is provided between the source/drain electrodes and the organic semiconductor layer. A method of fabricating such an organic thin film transistor is also provided. According to example embodiments, the organic thin film transistor may have increased charge mobility and an Ion/Ioff ratio, due to decreased contact resistance between the source/drain electrodes and the organic semiconductor layer. Moreover, upon the formation of the organic semiconductor layer and insulating film, a wet process may be more easily applied, thus simplifying the fabrication process and decreasing the fabrication cost.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Kim, Bon Won Koo, Eun Kyung Lee, Sang Yoon Lee, Bang Lin Lee
  • Patent number: 7646030
    Abstract: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the structure thus obtained into individual flip chip type LED lighting devices.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: January 12, 2010
    Assignee: Neobulb Technologies, Inc.
    Inventors: Jeffrey Chen, Chung Zen Lin
  • Patent number: 7642120
    Abstract: Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method thereof. In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively patterned to form a plurality of photoresist patterns. A surface of each photoresist is hardened. The hardened photoresist patterns are reflowed to form microlenses.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yeong Sil Kim
  • Patent number: 7642124
    Abstract: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: January 5, 2010
    Assignee: OrganicID, Inc.
    Inventors: Klaus Dimmler, Robert R. Rotzoll
  • Patent number: 7638377
    Abstract: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions are kept within a predetermined range. A laser beam having a wave length region, which can give more energy to the amorphous region than to the crystal region, is irradiated to the first polycrystalline semiconductor film, it is possible to crystallize the amorphous region without destroying the crystal region. If a TFT is manufactured based on a second polycrystalline semiconductor film, which is obtained through the above-mentioned crystallization processes, the TFT with high electric characteristics and less fluctuation can be obtained.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hideto Ohnuma, Chiho Kokubo
  • Patent number: 7638362
    Abstract: A memory module of the present invention has a memory core chip for storing information, an interface chip for controlling data input/output, an interposer chip for transmitting/receiving data to/from the outside, and an external connection terminal provided in closest proximity to the interposer chip. A heat dissipating plate is provided in closest proximity to the interface chip. The interposer chip has a substrate made of a semiconductor material that is similar to the memory core chip, a land for holding the external connection terminal, a wire connected to the external connection terminal, and an insulating film for insulating the wire. The land, wire, and insulating film are integrally formed on one surface of the interposer chip.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: December 29, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda