Abstract: A method and apparatus of a device that performs a generalized moment based variation aware timing analysis on a circuit design is described. The device receives a signal path that traverses a plurality of gates. For each of the plurality of gates, the device retrieves a statistical distribution that represents delay variation at the gate. The statistical distribution for each gate is measured by a number of statistical moments that include higher order statistical moments besides the mean and the standard deviation of the distribution. The device computes statistical moments to represent the timing variation on the signal path by propagating statistical distributions of the gates on the signal path. The device reconstructs a statistical distribution function for timing variation on the signal path based on the computed statistical moments.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.

Abstract: One method implementation disclosed includes detecting matching leaf cells that have functionally identical designs (optionally, similar designs) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy.

Abstract: Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Abstract: A method and system for fracturing or mask data preparation or proximity effect correction is disclosed in which a series of charged particle beam shots is determined, where the series of shots is capable of forming a continuous non-manhattan track on a surface, such that the non-manhattan track has a line width roughness (LWR) which nearly equals a target LWR. A method and system for fracturing or mask data preparation or proximity effect correction is also disclosed in which at least two series of shots are determined, where each series of shots is capable of forming a continuous non-manhattan track on a surface, and where the space between tracks has space width roughness (SWR) which nearly equals a target SWR.

Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.

Abstract: Disclosed are systems and methods for improving quantum computation simulation execution time by “growing” sets of small quantum gates into larger ones. Two approaches are described. In the first approach, sub-strings may be replaced by a single representative that may be used multiple times throughout the quantum circuit. In the second approach, nearby gates may be coalesced in an iterative fashion, to thereby build larger and larger gates. Results may be cached for re-use. Both of these approaches have proven effective and have gained typical simulation speed-ups of 1-2 orders of magnitude.

Abstract: A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.

Abstract: A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.

Abstract: Embodiments of the disclosure relate to methods for facilitating the design of an integrated circuit (IC) using thermally aware pin assignment and device placement. The method includes creating a layout for the IC, the layout including a plurality of macros each having devices and pin assignments and revising the layout for the IC by repositioning a macro or a device to meet a timing requirement of the IC. The method also includes creating a thermal map of the IC based on the layout for the IC and a workload model for the IC and identifying at least one thermally critical pin assignment based on the thermal map of the IC. The method includes revising the layout by repositioning a thermally critical pin assignment and a device.

Abstract: A charging control apparatus (1) that controls charging of a plurality of vehicles connected via a power line is provided with an electrical storage section (41) that stores power supplied from a power source, a communication section that receives information relating to supply power from the plurality of vehicles, a power amount calculation section (43) that calculates a supply power amount for the plurality of vehicles based on the information, and a control section that, if the supply power amount exceeds a second threshold value combining a remaining charge amount of the electrical storage section (41) and a contractual power amount, controls supply power for the plurality of vehicles so as to become smaller than the second threshold value.

Abstract: In one aspect, a technique for performing signal activity extraction in an integrated circuit an integrated circuit is described. The integrated circuit includes multiple nodes. The technique includes compiling a design of the integrated circuit, estimating signal activities at the nodes, determining a node of interest from the nodes, and connecting a signal activity circuit to the node of interest. The determination of the node of interest and the connection of the signal activity circuit to the node of interest first compared to the remaining nodes of the integrated circuit improves efficiency in determining nodes of the integrated circuit at which signals can be analyzed first. Such signal activity extraction may involve power analysis and power optimization.

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.

Abstract: Disclosed is a handheld electronic device with positioning function that includes a device body that contains a transceiver circuit module, a positioning element, and a counterpart positioning element that corresponds to the positioning element in order to effect mutual positioning with respect to each other. The positioning element and the counterpart positioning element are both mounted to one side of the device body. Through rotating or putting up-side down one of two handheld electronic devices, the two handheld electronic devices can be positioned with respect to each other through the positioning elements and the counterpart positioning elements so as to have the transceiver circuit modules of the two handheld electronic devices precisely aligning with each other.

Abstract: Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.

Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

Abstract: An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface comprising a data table is generated to assist a user to configure pin settings. A user setting is obtained via the pin-editing interface, and a schematic diagram is generated on a display unit according to the obtained user setting.

Abstract: Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.

Abstract: Provided is a vehicle battery-pack equalization system (100), wherein, in a battery pack (10) to be mounted on a vehicle, and which is comprised of a plurality of unit cells (11) connected in series, each of the unit cells (11) are made to be discharged to equalize the voltages thereof, or the remaining capacities (SOC) thereof. The equalization processing time of each of the unit cells (11) is set to a period of time the result of multiplying the discharging time of the battery pack (10) starting from just before the equalization processing, and the ratio of the difference between the currents discharged by each of the unit cells (11) with respect to the equalization discharging current. In such a way, power consumption during equalization processing can be inhibited.

Abstract: A charging apparatus 10 includes: a half-wave rectifier 21 that half-wave rectifies an alternating current supplied from a commercial power supply 11; a radiofrequency generating circuit 22 that converts the output current of the half-wave rectifier 21 to a radiofrequency current with a predetermined frequency and outputs the radiofrequency current; an induction coil 23 that is fed with the radiofrequency current from the radiofrequency generating circuit 22; a power receiving coil 24 that receives an electromotive force induced by a magnetic flux produced on the induction coil 23; a resonant capacitor 25 that is connected in parallel with the power receiving coil 24 and forms a resonant circuit with the power receiving coil 24 at the predetermined frequency; and a full-wave rectifier 27 that full-wave rectifies the output current of the parallel resonant circuit and supplies the current to a lead storage battery 12.