Patents Examined by Mahmoud Dahimene
  • Patent number: 11270892
    Abstract: A microfabrication process includes: (1) etching a shield pattern into a substrate; (2) forming a set of shielding layers on the substrate and in the shield pattern, wherein the shielding layers include n+1 magnetic layers and n spacing layers, n is 0 or an integer that is 1 or greater than 1, and each spacing layer is disposed between a pair of magnetic layers; and (3) planarizing the substrate to expose edges of the shielding layers.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 8, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Robert N. Candler, Jimmy Chen-Yen Wu, Ling Li, Jere C. Harrison
  • Patent number: 11239090
    Abstract: A plasma processing method executed by a plasma processing apparatus includes steps of an opening formation, a first film formation, a second film formation, and an etching. In the opening formation, the plasma processing apparatus performs etching on a substrate including a base layer and a first layer formed on the base layer so as to form an opening in the first layer. When determined that the opening satisfies a predetermined condition, in the first film formation, the plasma processing apparatus forms an inhibitor on a bottom surface of the opening so as to form a first film to which a predetermined gas species is not adsorbed. After the formation of the first film, the plasma processing apparatus forms a second film on the side wall of the opening in the second film formation. The plasma processing apparatus also performs etching in the opening in the etching.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Sho Kumakura
  • Patent number: 11225044
    Abstract: A method for forming a porous copper composite is provided. At least two carbon nanostructure reinforced copper composite substrates are provided. The at least two carbon nanostructure reinforced copper composite substrates are stacked to form a composite substrate. An active metal layer is disposed on a surface of the composite substrate to form a first a composite structure. The first composite structure is pressed to form a second composite structure. The second composite structure is annealed to form a third composite structure. The third composite structure is de-alloyed to form a porous copper composite.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 18, 2022
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yuan-Feng Liu, Ze-Cheng Hou, Lu Chen, Lin Zhu, Wen-Zhen Li
  • Patent number: 11220752
    Abstract: A process for surface treatment of semi-finished aluminum products is provided. The process includes preparing an aqueous solution of sodium hydroxide (NaOH) and dissolved metallic aluminum, kept in suspension by adding complexing agents including gluconate and sorbitol, and placing a semi-finished aluminum product in contact with the aqueous solution, maintaining temperature of the aqueous solution within a predetermined range.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 11, 2022
    Inventor: Claudio Marenco
  • Patent number: 11189498
    Abstract: There is provided a method of etching a silicon-containing film formed on a substrate, the method including: etching the silicon-containing film by using both a first fluorine-containing gas and a second fluorine-containing gas, the first fluorine-containing gas including at least an F2 gas and the second fluorine-containing gas including at least a ClF3 gas, an IF7 gas, an IF5 gas or an SF6 gas.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takehiko Orii, Yasuo Asada, Jun Lin, Ayano Hagiwara, Shinji Irie, Kenji Tanouchi, Kakeru Wada
  • Patent number: 11189497
    Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
  • Patent number: 11189499
    Abstract: Methods for the atomic layer etch (ALE) of tungsten or other metal layers are disclosed that use in part sequential oxidation and reduction of tungsten/metal layers to achieve target etch parameters. For one embodiment, a metal layer is first oxidized to form a metal oxide layer and an underlying metal layer. The metal oxide layer is then reduced to form a surface metal layer and an underlying metal oxide layer. The surface metal layer is then removed to leave the underlying metal oxide layer and the underlying metal layer. Further, the oxidizing, reducing, and removing processes can be repeated to achieve a target etch depth. In addition, a target etch rate can also achieved for each process cycle of oxidizing, reducing, and removing.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yu-Hao Tsai, Du Zhang, Mingmei Wang, Aelan Mosden, Matthew Flaugh
  • Patent number: 11180678
    Abstract: Present invention provides Chemical Mechanical Planarization Polishing (CMP) compositions for Shallow Trench Isolation (STI) applications. The CMP compositions contain ceria coated inorganic oxide particles as abrasives, such as ceria-coated silica particles; chemical additive selected from the group consisting of an organic acetylene molecule containing an acetylene bond and at least two or multi ethoxylate functional groups with terminal hydroxyl groups, an organic molecule with at least two or multi hydroxyl functional groups in the same molecule, and combinations thereof; water soluble solvent; and optionally biocide and pH adjuster; wherein the composition has a pH of 2 to 12, preferably 3 to 10, and more preferably 4 to 9.
    Type: Grant
    Filed: October 27, 2019
    Date of Patent: November 23, 2021
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xiaobo Shi, Krishna P. Murella, Joseph D. Rose, Hongjun Zhou, Mark Leonard O'Neill
  • Patent number: 11183383
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick van Cleemput, Bart J. van Schravendijk
  • Patent number: 11149201
    Abstract: Provided is a silicon nitride layer etching composition, and more specifically, a silicon nitride layer etching composition including two different silicon-based compounds in an etching composition to be capable of selectively etching a silicon nitride layer relative to a silicon oxide layer with a remarkable etch selectivity ratio and providing remarkable effects of suppressing generation of precipitates and reducing the abnormal growth of other layers existing in the vicinity, including the silicon oxide layer when the silicon nitride layer etching composition is used for an etching process and a semiconductor manufacturing process.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 19, 2021
    Assignee: ENF TECHNOLOGY CO., LTD.
    Inventors: Dong Hyun Kim, Hyeon Woo Park, Du Won Lee, Jang Woo Cho, Myung Ho Lee, Myung Geun Song
  • Patent number: 11120986
    Abstract: A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping Lin, Yi-Wei Chiu, Tzu-Chan Weng, Wen-Zhong Ho
  • Patent number: 11107682
    Abstract: A method of patterning a substrate includes forming mandrels on a target layer of a substrate, the mandrels being comprised of at least two layers of material, the mandrels including a bottom layer comprised of a first material, and a top layer comprised of a second material, the target layer being comprised of a fifth material. The method includes forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers comprised of a third material. The method includes depositing a fill material on the substrate that at least partially fills open spaces defined between the sidewall spacers, the fill material being comprised of a fourth material. The method includes executing a chemical-mechanical polishing step that uses the bottom layer of the mandrels as a planarization stop material layer, the chemical-mechanical polishing step removing the third material above a top surface of the bottom layer of the mandrels.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 31, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 11094554
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen. The wafer includes a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The method also includes polishing the wafer using a first operation to thin down the metal layer. The first operation has a first polishing selectivity of the metal layer to the dielectric layer. The method further includes polishing the wafer using a second operation to further thin down the metal layer until the dielectric layer is exposed. The second operation has a second polishing selectivity of the metal layer to the dielectric layer. The second polishing selectivity is different from the first polishing selectivity. The first operation and the second operation are performed in-situ on the polishing platen.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ho Lin, Jen-Chieh Lai, Jheng-Si Su, Zhi-Sheng Hsu, Po-Ting Huang
  • Patent number: 11081361
    Abstract: Provided is a plasma etching method comprising supplying both hexafluoroisopropanol (HFIP) gas and argon (Ar) gas to a plasma chamber receiving an etching target therein, thereby to plasma-etch the etching target.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 3, 2021
    Assignee: AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Chang-Koo Kim, Jun-Hyun Kim, Jin-Su Park
  • Patent number: 11066575
    Abstract: Chemical mechanical polishing (CMP) compositions, systems and methods of using the compositions for polishing tungsten or tungsten-containing substrates. The compositions comprise nano-sized abrasive; metal compound coated organic polymer particles as solid state catalyst; oxidizer; tungsten corrosion inhibitor; and a water based liquid carrier.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Versum Materials US, LLC
    Inventors: Xiaobo Shi, Hongjun Zhou, James Allen Schlueter, Jo-Ann T. Schwartz
  • Patent number: 11066328
    Abstract: A low reflectivity coating (20) is formed of a layer of carbon nanostructures (20) over a contact surface (14) of a substrate (10), from a spray incorporating the carbon nanostructures in suspension in a solvent. The carbon nanostructure layer provides a very low reflectivity coating which may be further enhanced by etching the outer surface of the coating. The layer may be etched for reduced reflectivity. Very low reflectivity coatings have been achieved.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 20, 2021
    Assignee: SURREY NANOSYSTEMS LIMITED
    Inventor: Ben Poul Jensen
  • Patent number: 11062912
    Abstract: A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 13, 2021
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventor: Shawming Ma
  • Patent number: 11056370
    Abstract: A method according to an embodiment includes: (a) a first step of etching a workpiece held by a holding structure in a state in which a first direction and a second direction are maintained to form a first angle, by a plasma generated in a processing container; and (a) a second step of, after execution of the first step, etching the workpiece held by the holding structure in a state in which the first direction and the second direction are maintained to form a second angle, by the plasma generated in the processing container.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shuhei Ogawa, Keigo Toyoda, Yoshihide Kihara
  • Patent number: 11053440
    Abstract: Compositions useful for the selective removal of silicon nitride materials relative to polysilicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon are provided. The compositions of the invention are particularly useful in the etching of 3D NAND structures.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 6, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Steven M. Bilodeau, SeongJin Hong, Hsing-Chen Wu, Min-Chieh Yang, Emanuel I. Cooper
  • Patent number: 11056349
    Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Hiroshi Okuno, Reiji Niino, Hiroyuki Hashimoto, Tatsuya Yamaguchi