Patents Examined by Mahmoud Dahimene
  • Patent number: 10370529
    Abstract: Provided is a method of manufacturing a patterned substrate. The method may be applied to a process of manufacturing a device such as an electronic device or integrated circuit, or another use, for example, to manufacture an integrated optical system, a guidance and detection pattern of a magnetic domain memory, a flat panel display, a LCD, a thin film magnetic head or an organic light emitting diode, and used to construct a pattern on a surface to be used to manufacture a discrete tract medium such as an integrated circuit, a bit-patterned medium and/or a magnetic storage device such as a hard drive.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 6, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Se Jin Ku, Mi Sook Lee, Hyung Ju Ryu, Jung Keun Kim, Sung Soo Yoon, No Jin Park, Je Gwon Lee, Eun Young Choi
  • Patent number: 10354888
    Abstract: Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl2 plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl2 plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Huai-Yu Hsiao
  • Patent number: 10354875
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: July 16, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Patent number: 10347497
    Abstract: A method of catalyst-assisted chemical etching with a vapor-phase etchant has been developed. In one approach, a semiconductor substrate including a patterned titanium nitride layer thereon is heated, and an oxidant and an acid are evaporated to form a vapor-phase etchant comprising an oxidant vapor and an acid vapor. The semiconductor substrate and the patterned titanium nitride layer are exposed to the vapor-phase etchant during the heating of the semiconductor substrate. The vapor-phase etchant diffuses through the patterned titanium nitride layer, and titanium nitride-covered regions of the semiconductor substrate are etched. Thus, an etched semiconductor structure is formed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 9, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Jeong Dong Kim
  • Patent number: 10347499
    Abstract: In a method of an embodiment, radicals, which are generated from a processing gas, is adsorbed to a layer to be etched without applying a high-frequency bias to a lower electrode, in an adsorption step. In the subsequent etching step, ions, which are generated from the processing gas, are drawn into the layer to be etched by applying a high-frequency bias to the lower electrode. The adsorption step and the etching step are alternately repeated. In the adsorption step, a density of radicals is 200 or greater times a density of ions. In the etching step, RF energy having a power density of 0.07 W/cm2 or less is supplied to the lower electrode or a high-frequency bias having a power density of 0.14 W/cm2 or less is supplied to the lower electrode for a period of 0.5 seconds or less.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Maruyama, Akira Koshiishi, Toshio Haga, Masato Horiguchi, Makoto Kato
  • Patent number: 10332906
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori Narumiya, Hisataka Hayashi, Keisuke Kikutani, Akio Ui, Yosuke Sato
  • Patent number: 10310373
    Abstract: A method for manufacturing a low-defect and high-quality mask blank substrate with minimized transfer pattern defects and high mechanical strength, particularly such that the occurrence of a phenomenon where a portion of a transfer pattern and a principal surface of the substrate therebeneath are broken off together is minimized such that there is little pattern loss. The mask blank is manufactured by preparing a mask blank substrate (X) having a substrate principal surface (X1) polished using a polishing solution containing abrasive grains, etching the substrate principal surface (X1) using catalyst-referred etching so as to remove damaged portions from the principal surface (X1), and then depositing a thin film that forms a transfer pattern on the substrate principal surface (X1) of the substrate (X) by sputtering.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 4, 2019
    Assignee: HOYA CORPORATION
    Inventors: Takeyuki Yamada, Takahito Nishimura
  • Patent number: 10287430
    Abstract: Provided is a method of manufacturing a patterned substrate. The method may be applied to a process of manufacturing a device such as an electronic device or integrated circuit, or another use, for example, to manufacture an integrated optical system, a guidance and detection pattern of a magnetic domain memory, a flat panel display, a LCD, a thin film magnetic head or an organic light emitting diode, and used to construct a pattern on a surface to be used to manufacture a discrete tract medium such as an integrated circuit, a bit-patterned medium and/or a magnetic storage device such as a hard drive.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 14, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Se Jin Ku, Mi Sook Lee, Hyung Ju Ryu, Jung Keun Kim, Sung Soo Yoon, No Jin Park, Je Gwon Lee, Eun Young Choi
  • Patent number: 10283373
    Abstract: An embodiment of the present invention relates to a CMP polishing liquid used for polishing a polishing target surface having at least a cobalt-containing portion and a metal-containing portion that contains a metal other than cobalt, wherein the CMP polishing liquid contains polishing particles, a metal corrosion inhibitor and water, and has a pH of 4.0 or less, and when the corrosion potential EA of cobalt and the corrosion potential EB of the metal are measured in the CMP polishing liquid, the absolute value of the corrosion potential difference EA?EB between the corrosion potential EA and the corrosion potential EB is 0˜300 mV.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 7, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Masahiro Sakashita, Naomi Watanabe, Masayuki Hanano, Kouji Mishima
  • Patent number: 10283368
    Abstract: There is provided a plasma etching method for etching a base film by a plasma using a photoresist as a mask. The method includes etching the base film by the plasma, under a first processing condition in which a selectivity of the photoresist to the base film is set to a first selectivity, while using as a mask the photoresist formed in a predetermined pattern by exposure and development and a scum remaining in the photoresist, without performing a process of removing the scum; and switching, during the etching of the base film, the first processing condition to a second processing condition in which the selectivity of the photoresist to the base film is set to a second selectivity lower than the first selectivity and further etching the base film by a plasma while using the photoresist as a mask under the second processing condition.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 7, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shunichi Mikami
  • Patent number: 10276398
    Abstract: Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 30, 2019
    Assignee: Lam Research Corporation
    Inventors: Kwame Eason, Pilyeon Park, Mark Naoshi Kawaguchi, Seung-Ho Park, Hsiao-Wei Chang
  • Patent number: 10276372
    Abstract: A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10276381
    Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yi-Nien Su
  • Patent number: 10267962
    Abstract: A method of making a pine shaped metal nano-scaled grating, the method including: forming a first metal layer on a substrate, forming an isolation layer on the first metal layer, and locating a second metal layer on the isolation layer; placing a first mask layer on the second metal layer, wherein the first mask layer comprises a body, and the body defines a plurality of openings parallel with and spaced apart from each other; etching the first mask layer and the second metal layer to obtain a plurality of triangular prism structures; etching the isolation layer to obtain a plurality of second rectangular structures using the plurality of triangular prism structures as a first mask; and etching the first metal layer to obtain a plurality of first rectangular structures using the plurality of second rectangular structures as a second mask.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10260150
    Abstract: Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 16, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Luong, Akiteru Ko
  • Patent number: 10246781
    Abstract: A method for removing a metallic deposit disposed on a surface in a chamber, including the following steps: a) a step of oxidizing the metallic deposit; b) a step of injecting chemical species adapted to volatilized the oxidized metallic deposit, the step b) being implemented during at least a part of step a); and in step b), the chemical species are injected according to a sequence of pulses.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: April 2, 2019
    Inventors: Julien Vitiello, Jean-Luc Delcarri, Fabien Piallat
  • Patent number: 10242883
    Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Patent number: 10224209
    Abstract: An etching method according to an embodiment includes supplying an etchant containing hydrofluoric acid, an oxidizer, and a buffer to a semiconductor substrate including a first region covered with a metal layer made of one or more metals other than noble metals, and a second region covered with a catalyst layer made of a noble metal, such that the etchant comes in contact with the catalyst layer and the metal layer, thereby etching the semiconductor substrate at a position of the catalyst layer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 5, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Yusaku Asano
  • Patent number: 10217645
    Abstract: Chemical mechanical polishing (CMP) compositions, methods and systems for polish cobalt or cobalt-containing substrates are provided. Dual, or at least two chelators were used in the CMP polishing compositions as complexing agents for achieving the unique synergetic effects to afford high, tunable Co removal rates and with low static etch rates on Co film surface for the efficient Co corrosion protection during CMP process. The cobalt chemical mechanical polishing compositions also provide very high selectivity of Co film vs. other barrier layers, such as Ta, TaN, Ti, and TiN, and dielectric film, such as TEOS, SiNx, low-k, and ultra low-k films.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 26, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xiaobo Shi, James Allen Schlueter, Mark Leonard O'Neill
  • Patent number: 10197826
    Abstract: Electronic flat panel displays (FPDs) including liquid crystal displays (LCDs) may be resized to meet custom size requirements for applications in aerospace and elsewhere. During the resizing process, pixel line defects may occur in the image due to electrical short circuits at the resized cut edge. Methods for repairing such short circuits are described, including use of mechanical, electrical, chemical, thermal, and/or other methods, and any combination thereof, to open the short circuits. The methods may be applied to the sealed cut edge to ruggedize the seal, even if image defects are not exhibited initially. The repaired short circuits may be stress tested to ensure the defects will not recur during the life of the display, and the repaired areas may be resealed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 5, 2019
    Inventor: Lawrence E. Tannas, Jr.