Patents Examined by Mahmoud Dahimene
  • Patent number: 10197826
    Abstract: Electronic flat panel displays (FPDs) including liquid crystal displays (LCDs) may be resized to meet custom size requirements for applications in aerospace and elsewhere. During the resizing process, pixel line defects may occur in the image due to electrical short circuits at the resized cut edge. Methods for repairing such short circuits are described, including use of mechanical, electrical, chemical, thermal, and/or other methods, and any combination thereof, to open the short circuits. The methods may be applied to the sealed cut edge to ruggedize the seal, even if image defects are not exhibited initially. The repaired short circuits may be stress tested to ensure the defects will not recur during the life of the display, and the repaired areas may be resealed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 5, 2019
    Inventor: Lawrence E. Tannas, Jr.
  • Patent number: 10192749
    Abstract: According to the present invention, a dry-etching method for performing plasma etching in a vertical profile while maintaining selectivity relative to a mask, includes: a first process of etching a film to be etched with use of reactive gas to cause an etching profile of the film to be etched to be formed in a footing profile; and a second process of, after the first process, causing the footing profile to be formed in a vertical profile by means of sputtering etching.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: January 29, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kenichi Kuwahara, Syuji Enokida
  • Patent number: 10174427
    Abstract: The method for treatment of parts, characterized in that it comprises the stages of applying an electrolytic chromium plating layer on a part; applying a coating over the entire outer surface of the part; selective stripping of the coating in order to leave the part with at least one coated portion and at least one uncoated portion; carrying out a selective etching on the layer in at least one part of the uncoated portion; metallization of the entire surface of the part; and removal of the coating.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 8, 2019
    Assignee: ZANINI AUTO GRUP, S.A.
    Inventors: Augusto Mayer Pujadas, José Sanahuja Clot
  • Patent number: 10170335
    Abstract: A process for chemical mechanical polishing a substrate containing cobalt and TiN to at least improve cobalt: TiN removal rate selectivity. The process includes providing a substrate containing cobalt and TiN; providing a polishing composition, containing, as initial components: water; an oxidizing agent; alanine or salts thereof; and, colloidal silica abrasives with diameters of ?25 nm; and, providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the cobalt is polished away such that there is an improvement in the cobalt: TiN removal rate selectivity.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: January 1, 2019
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Murali G. Theivanayagam, Hongyu Wang, Matthew Van Hanehem
  • Patent number: 10141187
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 27, 2018
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 10134600
    Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Leonid Romm, Alan Jensen, Xin Zhang, Gerardo Delgadino
  • Patent number: 10103019
    Abstract: The present invention provides a method of fabricating a semiconductor structure. Firstly, a substrate is provided, a dense region and an isolation region are defined, next, a first dielectric layer is formed on the dense region and the isolation region, and then a plurality of first recesses are formed in the first dielectric layer within the dense region, and a second recess is formed in the first dielectric layer within the isolation region, wherein the width of the second recess is greater than three times of the width of each first recess. Afterwards, a second dielectric layer is then filled in each first recess and the second recess, wherein a top surface of the second dielectric layer within the isolation region is higher than a top surface of the second dielectric layer within the dense region. Next, an etching back process is performed, to remove the second dielectric layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 16, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10093834
    Abstract: There are provided a polishing composition and a method for polishing capable of, when a substrate including polysilicon is polished, limiting the polishing rate of the polysilicon, and selectively polishing a silicon compound other than the polysilicon, such as silicon nitride. The polishing composition used includes abrasives, an organic acid and a conjugate base of the organic acid.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 9, 2018
    Inventor: Yasuto Ishida
  • Patent number: 10079382
    Abstract: A method of forming an electrode in an electrochemical battery comprises: coating a reticulated substrate with a conductive material; curing the reticulated substrate coated with the conductive material; and electroplating the reticulated substrate coated with the conductive material with a desired metal material.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 18, 2018
    Inventors: Alvin Snaper, Jonathan Jan
  • Patent number: 10049876
    Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10037889
    Abstract: The present invention provides methods for chemical mechanical polishing (CMP polishing) spin coated organic polymer films on a semiconductor wafer or substrate as part of lithography or as part of electronic packaging. The methods comprising spin coating an organic polymer liquid on a semiconductor wafer or substrate; at least partially curing the spin coating to form an organic polymer film; and, CMP polishing the organic polymer film with a polishing pad and an aqueous CMP polishing composition having a pH ranging from 1.5 to 4.5 and comprising elongated, bent or nodular silica particles containing one or more cationic nitrogen or phosphorus atoms, from 0.005 to 0.5 wt. %, based on total CMP polishing composition solids, of a sulfate group containing C8 to C18 alkyl or alkenyl group surfactant, and a pH adjusting agent.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 31, 2018
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Julia Kozhukh, Lee Melbourne Cook, Michael E. Mills
  • Patent number: 10037893
    Abstract: A method and apparatus for etching a wafer are provided. The method includes placing a first wafer with a first target material into a first chamber, and placing a second wafer with a second target material into a second chamber. The second chamber is connected to the first chamber by a first pipe. The method also includes applying a first Xe-containing gaseous etchant into the first chamber to etch the first target material. A portion of the first Xe-containing gaseous etchant in the first chamber is unreacted during the etching of the first target material. The method further includes applying the unreacted portion of the first Xe-containing gaseous etchant from the first chamber into the second chamber through the first pipe to etch the second target material of the second wafer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 31, 2018
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu
  • Patent number: 10032605
    Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 24, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 10005100
    Abstract: A method of forming fine patterns includes the steps of forming a conductive layer on a base part, forming a sacrificial layer including an adhesive material on the conductive layer, the adhesive material including a catechol group, forming resist patterns on the sacrificial layer, and forming fine patterns by patterning the conductive layer using the resist patterns as a mask.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eun Ae Kwak, Min Hyuck Kang, Gug Rae Jo
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 10002754
    Abstract: Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 19, 2018
    Inventor: Keiichi Tanaka
  • Patent number: 9994737
    Abstract: Provided are slurry compounds for polishing an SOH organic layer and methods of fabricating a semiconductor device using the same. The slurry compound may include a polishing particle, an oxidizing agent including at least one selected from the group consisting of a nitrate, a sulfate, a chlorate, a perchlorate, a chlorine, and a peroxide, and a polishing accelerator.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyun Kim, Yun-Jeong Kim, SeungHo Park
  • Patent number: 9966263
    Abstract: A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: May 8, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Ju Li, Li-Chieh Hsu, Yi-Han Liao, Chun-Tsen Lu, Chih-Hsun Lin, Hsin-Jung Liu
  • Patent number: 9966273
    Abstract: There is provided a plasma etching method. The plasma etching method includes generating plasma, by using a first high frequency power output from a first high frequency power supply, from a first processing gas that contains fluorine-containing gas, thereby etching a laminated film of a silicon oxide film and a silicon nitride film through the generated plasma, and generating plasma, by using the first high frequency power, from a second processing gas that contains bromine-containing gas, thereby etching the laminated film through the generated plasma.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 8, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Takayama, Sho Tominaga, Yoshiki Igarashi
  • Patent number: 9958769
    Abstract: A plasmon generator including a wide portion and a narrow portion is manufactured by etching an initial plasmon generator using an etching mask. The etching mask includes a first mask layer for defining the shape of one of the narrow portion and the wide portion, and a second mask layer for defining the shape of the other of the narrow portion and the wide portion. The etching mask is formed by forming a first hard mask, a second initial mask layer and a second hard mask in this order on a first initial mask layer, and etching the first and second initial mask layers by using the first and second hard masks.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 1, 2018
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Seiichiro Tomita, Shigeki Tanemura, Yukinori Ikegawa