Patents Examined by Mahmoud Dahimene
  • Patent number: 11043380
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 22, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 11043151
    Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive selected from the group consisting of alumina, ceria, titania, zirconia, and combinations thereof, wherein the abrasive is surface-coated with a copolymer comprising a combination of sulfonic acid monomeric units and carboxylic acid monomeric units a combination of sulfonic acid monomeric units and phosphonic acid monomeric units, (b) an oxidizing agent, and (c) water, wherein the polishing composition has a pH of about 2 to about 5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate comprises tungsten or cobalt and silicon oxide.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 22, 2021
    Assignee: CMC Materials, Inc.
    Inventors: Ji Cui, Helin Huang, Kevin P. Dockery, Pankaj K. Singh, Hung-Tsung Huang, Chih-Hsien Chien
  • Patent number: 11031245
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 8, 2021
    Assignee: Lan Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
  • Patent number: 11024514
    Abstract: There is provided an etching method including: loading a substrate having a recess and an etching target portion existing on an inner surface of the recess into a processing container, the etching target portion being made of SiN or Si; preferentially modifying a surface of the etching target portion at a top portion of the recess by performing an oxygen-containing plasma process on the substrate inside the processing container; and subsequently, dry-etching the etching target portion in an isotropic manner.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 1, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takuya Abe, Hidenori Miyoshi, Akitaka Shimizu, Koichi Nagakura
  • Patent number: 11011383
    Abstract: There is provided an etching method which includes: supplying an etching gas to a workpiece including a first SiGe-based material and a second SiGe-based material having different Ge concentrations; and selectively etching the first SiGe-based material and the second SiGe-based material with respect to the other using a difference in incubation time until the first SiGe-based material and the second SiGe-based material begin to be etched by the etching gas.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 18, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasuo Asada, Takehiko Orii, Nobuhiro Takahashi
  • Patent number: 11011385
    Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
  • Patent number: 10998198
    Abstract: There is provided a substrate processing method for performing an etching processing by immersing a substrate in a processing liquid containing a chemical liquid and silicon, the substrate processing method including: a preparation step of setting a supply flow rate of the chemical liquid based on a replenishment amount of the chemical liquid and a replenishment amount of the silicon; and a replenishment step of supplying the chemical liquid at the set supply flow rate of the chemical liquid and dissolving a set replenishment amount of the silicon in the processing liquid.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 4, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kazuya Koyama
  • Patent number: 10971372
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Subhadeep Kal, Nihar Mohanty, Angelique D. Raley, Aelan Mosden, Scott W. Lefevre
  • Patent number: 10954411
    Abstract: An acid chemical mechanical polishing composition polishes silicon nitride over silicon dioxide and simultaneously inhibits damage to the silicon dioxide. The acid chemical mechanical polishing composition includes polyvinylpyrrolidone polymers, anionic functional colloidal silica abrasive particles and an amine carboxylic acid. The pH of the acid chemical mechanical polishing composition is 5 or less.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 23, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventors: Naresh Kumar Penta, Kwadwo E. Tettey, Matthew Van Hanehem
  • Patent number: 10957547
    Abstract: Compositions useful for the selective removal of silicon germanium materials relative to germanium-containing materials and silicon-containing materials from a microelectronic device having same thereon. The removal compositions include at least one diol and are tunable to achieve the required SiGe:Ge removal selectivity and etch rates.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 23, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Steven Bilodeau, Emanuel I. Cooper
  • Patent number: 10957554
    Abstract: Disclosed is a dry etching method for etching a metal film on a substrate with the use of an etching gas, wherein the etching gas contains a ?-diketone and first and second additive gases; wherein the metal film contains a metal element capable of forming a complex with the ?-diketone; wherein the first additive gas is at least one kind of gas selected from the group consisting of NO, NO2, O2 and O3; wherein the second additive gas is at least one kind of gas selected from the group consisting of H2O and H2O2; wherein the amount of the ?-diketone contained is 10 vol % to 90 vol % relative to the etching gas; and wherein the amount of the second additive gas contained is 0.1 vol % to 15 vol % relative to the etching gas. The etching rate of the metal film is increased by this etching method.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 23, 2021
    Assignee: Central Glass Company, Limited
    Inventors: Kunihiro Yamauchi, Takashi Masuda, Akifumi Yao
  • Patent number: 10950458
    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasutaka Hama, Shinya Morikita, Kiyohito Ito
  • Patent number: 10950454
    Abstract: A method for etching a substrate includes performing, in a plasma chamber, a first etch of a substrate material using a plasma etch process. The first etch forms features to a first depth in the material. Following the first etch, the method includes performing, in the plasma chamber without removing the substrate from the chamber, an atomic layer passivation (ALP) process to deposit a conformal film of passivation over the mask and the features formed during the first etch. The ALP process uses a vapor from a liquid precursor to form passivation over the features and the mask. The method further includes performing, in the plasma chamber, a second etch of the material using the plasma etch process. The conformal film of passivation is configured to protect the mask and sidewalls of the features during the second etch. A plasma processing system also is described.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 16, 2021
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Tom A. Kamp, Yoshie Kimura, Duming Zhang, Chen Xu, John Drewery, Alex Paterson
  • Patent number: 10941342
    Abstract: An etchant composition may include: a peroxosulfate; a cyclic amine compound; a first amphoteric compound including a carboxyl group; and a second amphoteric compound including a sulfone group, wherein the second amphoteric compound may be different from the first amphoteric compound.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bong Kyun Kim, Jin Suek Kim, Seung Bo Shim, Shin Hyuk Choi, Seung Hee Kim, Dong Hee Lee, In Seol Kuk, Beom Soo Kim, Sang Tae Kim, Young Chul Park, Young Jin Yoon, Dae Sung Lim
  • Patent number: 10923356
    Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a silicon-germanium alloy and at least one other material, the silicon-germanium alloy represented as SixGe1-x, wherein x is a real number ranging from 0 to 1; and selectively etching the silicon-germanium alloy relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound, such as a diatomic halogen or an interhalogen compound.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Subhadeep Kal, Masashi Matsumoto, Daisuke Ito, Yusuke Muraki, Aelan Mosden
  • Patent number: 10903083
    Abstract: There is provided a substrate processing method which includes: treating a substrate using a fluorine-containing gas; and exposing the substrate to a moisture-containing atmosphere.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 26, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keiko Hada, Akitaka Shimizu, Koichi Nagakura, Mitsuhiro Tachibana
  • Patent number: 10886138
    Abstract: An etching shape can be suppressed from having non-uniform pattern. A substrate processing method includes burying an organic film in a recess surrounded by a silicon-containing film formed on a sidewall of a pattern of photoresist on a target film; and etching or sputtering the organic film and the silicon-containing film under a condition in which a selectivity thereof is about 1:1.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 5, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Timothy Tianshyun Yang, Shinya Morikita, Kiyohito Ito, Michiko Nakaya, Masanobu Honda
  • Patent number: 10886136
    Abstract: A method for processing a substrate in a plasma chamber is provided. The method includes providing a substrate on which an underlying layer to be etched and a mask are formed. The method further includes forming a protective film on the mask. The method further includes performing an anisotropic deposition to selectively form a deposition layer on a top portion of the mask.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 5, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Masanobu Honda, Yoshihide Kihara
  • Patent number: 10879066
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 29, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 10863629
    Abstract: A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 8, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kiyoyuki Hatanaka, Shigeru Sugino, Takahiro Kitagawa, Ryo Kanai, Nobuo Taketomi, Mitsunori Abe