Patents Examined by Mahmoud Dahimene
  • Patent number: 10501660
    Abstract: Provided is a slurry composition including abrasive particles, halogen oxide, and nitroxide compound. The combination of halogen oxide and nitroxide compound has a synergistic effect to remove a substrate containing tungsten and silicon oxide. Moreover, a use of the slurry composition and a polishing method using the slurry composition are provided.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 10, 2019
    Assignee: UWIZ Technology Co., Ltd.
    Inventors: Yun-Lung Ho, Chung-Wei Chiang, Song-Yuan Chang, Ming-Hui Lu, Ming-Che Ho
  • Patent number: 10504740
    Abstract: Provided is a method of removing a silicon oxide film of a workpiece having an insulating film and the silicon oxide film exposed at a bottom portion of an opening formed in the insulating film, including: forming a protective film containing carbon on a surface of the workpiece, wherein the protective film has a first region extending along a side wall surface of the insulating film that defines the opening and a second region extending on the silicon oxide film: removing the second region of the protective film and the silicon oxide film by sputter etching with ions from plasma of a first inert gas; and removing a residue of the silicon oxide film by chemical etching. The step of forming the protective film includes executing a plurality of cycles.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 10, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hideaki Yamasaki, Takamichi Kikuchi, Seishi Murakami
  • Patent number: 10504902
    Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Hyun Kim, Seung Pil Ko, Hyunchul Shin, Kilho Lee
  • Patent number: 10504743
    Abstract: A method of etching a film of a workpiece, which includes: measuring a second flow rate of a first gas based on an increase rate of an internal pressure of a first chamber in a state in which a valve is closed and the first gas is supplied into the first chamber at a first flow rate adjusted by a flow rate controller, and calibrating the flow rate controller using the measured second flow rate; supplying a second gas into the first chamber; exhausting the first chamber; supplying a mixed gas of the first and second gases into the first chamber with the workpiece not mounted on a stage; forming a reaction product from the film by supplying the mixed gas into the first chamber with the workpiece mounted on the stage; and removing the reaction product by heating the workpiece with the workpiece accommodated in a second chamber.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 10, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Motoko Nakagomi, Kohichi Satoh
  • Patent number: 10504720
    Abstract: A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping Lin, Yi-Wei Chiu, Tzu-Chan Weng, Wen-Zhong Ho
  • Patent number: 10497575
    Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 3, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Jeffrey Shearer
  • Patent number: 10483135
    Abstract: An etching method for a target object. The target object includes a main surface, grooves formed in the main surface, and an etching target film covering the main surface and surfaces of the grooves. The method includes supplying a first gas into a processing chamber, and supplying a second gas and a high frequency power to generate a plasma of a gas including the second gas in the processing chamber. The first gas contains an oxidizing agent that does not include a hydrogen atom. The second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom. The etching target film is made of a material that is dry etched by using fluorine, and portions of the etching target film covering the surfaces of the grooves are selectively removed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 19, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kenji Ouchi
  • Patent number: 10468273
    Abstract: A substrate processing method in a substrate processing apparatus that has a cup part for receiving processing liquid such as pure water which is splashed from a substrate. The cup part is formed of electrical insulation material. Hydrophilic treatment may be performed on an outer annular surface of the cup part. Water is held on at least one surface of the cup part while processing the substrate. The water maybe substantially grounded. With the disclosed method, charged potential of the cup part generated by splashing of pure water can be suppressed, without greatly increasing the manufacturing cost of the substrate processing apparatus. As a result, it is possible to prevent electric discharge from occurring on the substrate due to induction charging of the substrate, in application of the processing liquid onto the substrate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 5, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Masahiro Miyagi, Masanobu Sato, Hiroyuki Araki
  • Patent number: 10468266
    Abstract: A dry etching method includes performing at least two etching steps, and further includes injecting protective gas into an etch chamber for processing between any two successive etching steps, wherein the protective gas generates plasma to neutralize electrons accumulated on a side wall of an etching trench. According to the present disclosure, hydrogen plasma is added in an etching process to remove the electrons accumulated on the side wall of the etching trench so as to reduce the microetching effect in multiple etching. In this way, process stability and reliability of a display substrate are improved.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: November 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yinghai Ma, Liangjian Li, Yueping Zuo
  • Patent number: 10460946
    Abstract: A technique capable of removing a natural oxide film formed on a surface of a semiconductor layer which contains a compound of indium and an element other than indium as a main ingredient, without making a temperature of the semiconductor layer relatively high. The technique includes supplying a first etching gas which is ?-diketone to the semiconductor layer and heating the semiconductor layer to remove an oxide of the indium constituting the natural oxide film; and supplying a second etching gas to the semiconductor layer and heating the semiconductor layer to remove an oxide of the element constituting the natural oxide film. By using the first etching gas, it is possible to remove the indium oxide even if the temperature of the semiconductor layer is relatively low. This eliminates the need to increase the temperature to a relatively high level when removing the natural oxide film.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 29, 2019
    Assignees: TOKYO ELECTRON LIMITED, CENTRAL GLASS CO., LTD.
    Inventors: Jun Lin, Koji Takeya, Shinichi Kawaguchi, Mitsuhiro Tachibana, Akifumi Yao, Kunihiro Yamauchi
  • Patent number: 10460938
    Abstract: Techniques disclosed herein provide a method of patterning for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include forming bi-layer or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. The different materials can have different etch resistivities to be able to selectively etch one or more of the materials to create features and create cuts and blocks where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer. Having a mandrel of two or more layers of material enables one of those materials to be sacrificial such as when etching a spin-on reversal overcoat material that has filled-in open spaces, but leaves an overburden.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 29, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10453686
    Abstract: Methods and systems for in-situ spacer reshaping for self-aligned multi-patterning are described. In an embodiment, a method of forming a spacer pattern on a substrate may include providing a substrate with a spacer. The method may also include performing a passivation treatment to form a passivation layer on the spacer. Additionally, the method may include performing spacer reshaping treatment to reshape the spacer. The method may also include controlling the passivation treatment and spacer reshaping treatment in order to achieve spacer formation objectives.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Angelique Raley, Akiteru Ko
  • Patent number: 10410877
    Abstract: An etching method for etching a silicon oxide film is provided that includes generating a plasma from a gas including a hydrogen-containing gas and a fluorine-containing gas using a high frequency power for plasma generation, and etching the silicon oxide film using the generated plasma. The fluorine-containing gas includes a hydrofluorocarbon gas, and the sticking coefficient of radicals generated from the hydrofluorocarbon gas is higher than the sticking coefficient of radicals generated from carbon tetrafluoride (CF4).
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ryuichi Takashima, Taku Gohira, Yoshinobu Ooya
  • Patent number: 10370529
    Abstract: Provided is a method of manufacturing a patterned substrate. The method may be applied to a process of manufacturing a device such as an electronic device or integrated circuit, or another use, for example, to manufacture an integrated optical system, a guidance and detection pattern of a magnetic domain memory, a flat panel display, a LCD, a thin film magnetic head or an organic light emitting diode, and used to construct a pattern on a surface to be used to manufacture a discrete tract medium such as an integrated circuit, a bit-patterned medium and/or a magnetic storage device such as a hard drive.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 6, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Se Jin Ku, Mi Sook Lee, Hyung Ju Ryu, Jung Keun Kim, Sung Soo Yoon, No Jin Park, Je Gwon Lee, Eun Young Choi
  • Patent number: 10354888
    Abstract: Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl2 plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl2 plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Huai-Yu Hsiao
  • Patent number: 10354875
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: July 16, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Patent number: 10347497
    Abstract: A method of catalyst-assisted chemical etching with a vapor-phase etchant has been developed. In one approach, a semiconductor substrate including a patterned titanium nitride layer thereon is heated, and an oxidant and an acid are evaporated to form a vapor-phase etchant comprising an oxidant vapor and an acid vapor. The semiconductor substrate and the patterned titanium nitride layer are exposed to the vapor-phase etchant during the heating of the semiconductor substrate. The vapor-phase etchant diffuses through the patterned titanium nitride layer, and titanium nitride-covered regions of the semiconductor substrate are etched. Thus, an etched semiconductor structure is formed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 9, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Jeong Dong Kim
  • Patent number: 10347499
    Abstract: In a method of an embodiment, radicals, which are generated from a processing gas, is adsorbed to a layer to be etched without applying a high-frequency bias to a lower electrode, in an adsorption step. In the subsequent etching step, ions, which are generated from the processing gas, are drawn into the layer to be etched by applying a high-frequency bias to the lower electrode. The adsorption step and the etching step are alternately repeated. In the adsorption step, a density of radicals is 200 or greater times a density of ions. In the etching step, RF energy having a power density of 0.07 W/cm2 or less is supplied to the lower electrode or a high-frequency bias having a power density of 0.14 W/cm2 or less is supplied to the lower electrode for a period of 0.5 seconds or less.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Maruyama, Akira Koshiishi, Toshio Haga, Masato Horiguchi, Makoto Kato
  • Patent number: 10332906
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori Narumiya, Hisataka Hayashi, Keisuke Kikutani, Akio Ui, Yosuke Sato
  • Patent number: 10310373
    Abstract: A method for manufacturing a low-defect and high-quality mask blank substrate with minimized transfer pattern defects and high mechanical strength, particularly such that the occurrence of a phenomenon where a portion of a transfer pattern and a principal surface of the substrate therebeneath are broken off together is minimized such that there is little pattern loss. The mask blank is manufactured by preparing a mask blank substrate (X) having a substrate principal surface (X1) polished using a polishing solution containing abrasive grains, etching the substrate principal surface (X1) using catalyst-referred etching so as to remove damaged portions from the principal surface (X1), and then depositing a thin film that forms a transfer pattern on the substrate principal surface (X1) of the substrate (X) by sputtering.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: June 4, 2019
    Assignee: HOYA CORPORATION
    Inventors: Takeyuki Yamada, Takahito Nishimura