Abstract: A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or VSS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or VCC to a source of a P-channel FET transistor.
Abstract: A technique for forming high surface area electrode or storage nodes for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.
Abstract: A connectorized substrate and method of connectorizing a substrate is provided, including a substrate having conductive traces mounted thereon and solder paste connected to the conductive traces and conductive spheres mounted to the solder paste. The connectorized substrate of the present invention may be used to provide for components to be added to a motherboard such as a resistor network by mounting resistors to the conductive traces of the substrate such as thick-film ceramic resistors.
Abstract: A semiconductor layer is formed on a semiconductor substrate. A digital circuit region, in which a digital circuit is formed, and an analog circuit region, in which an analog circuit is formed, are separately formed by an isolation region at the surface of the semiconductor layer. At this time, a width of the semiconductor layer in the isolation region is greater than a thickness of the semiconductor substrate. Also, a region having high electrical resistance with low concentration of impurity is formed at the surface of the semiconductor substrate in the isolation region. Furthermore, conductive layers connected to a grounding potential is formed on the backside of the semiconductor substrate in the digital circuit region and on the backside of the semiconductor substrate of the analog region.
Abstract: An oxidation layer 44 for masking is formed on a PNP type transistor formation region 46a together with a field oxidation layer 42 for device separation. The oxidation layer 44 for masking is formed so as to cover an upper part of an active base formation region 52a located between the emitter/collector formation region 50a. The upper part of the active base formation region 52a which is not possible to adjust impurity concentration at processes carried out later is covered with the oxidation layer 44 for masking being formed relatively thick when boron B is implanted into a PMOS type transistor formation region 48a as channel ion. So that, boron is not implanted ionically to the active base formation region 52a. Therefore, it is not necessary to carry out masking process using photo resist layer in prior to boron implantation process.
Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.
Abstract: Electrode pads 6a are provided in the central portion of a semiconductor element 5, and the semiconductor element 5, which is mounted on a TCP tape 1 without device holes in this TCP tape, is mounted on the surface side of the TCP tape. In addition, the internal ends 2a of the wiring films 2 provided on the surface of the TCP tape 1 are extended all the way to the central portion of the semiconductor element 5 in conformity with these electrode pads 6a. The outside extension can be reduced and the TCP tape 1 shortened even when the wiring films 2 have the required length. In addition, the absence of device holes dispenses with the costs associated with punching out of the device holes, improves the mechanical strength of the wiring films 2, and enhances the holding force of the semiconductor element.
Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.
February 23, 1996
Date of Patent:
December 7, 1999
Ronald J. Jensen, Richard K. Spielberger, Toan Dinh Nguyen, William F. Jacobsen
Abstract: A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curable resin. An array of heat fins is bonded to the inactive surface of the wafer by a thermally conductive curable resin.
Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.
Abstract: An array (41) is comprised of a plurality of radiation detectors (10, 10') each of which includes a first photoresponsive diode (D1) having an anode and a cathode that is coupled to an anode of a second photoresponsive diode (D2). The first photoresponsive diode responds to electromagnetic radiation within a first band of wavelengths and the second photoresponsive diode responds to electromagnetic radiation within a second band of wavelengths. Each radiation detector further includes a first electrical contact (26) that is conductively coupled to the anode of the first photoresponsive diode; a second electrical contact (28) that is conductively coupled to the cathode of the first photoresponsive diode and to the anode of the second photoresponsive diode; and a third electrical contact (30) that is conductively coupled to a cathode of each second photoresponsive diode of the array. The electrical contacts are coupled during operation to respective bias potentials.
Abstract: A semiconductor package and method for preparing same to obtain improved die adhesion to organic chip carriers has been developed. A copper die bond pad is coated with a passivation material and attached to an organic card with the same passivation material. A semiconductor die may be adhered to the coated die bond pad with either the same passivation material or a common die bond adhesive. Alternatively, the passivation material is coated only on the portion of the die bond pad where the die is attached, and common die bond adhesive attaches the die bond pad to the organic card.
November 4, 1997
Date of Patent:
September 21, 1999
International Business Machines Corporation
Stephen John Kosteva, David Michael Passante, William John Rudik, David John Russell, Jonathan Craig Whitcomb
Abstract: A semiconductor processing method of forming integrated cicuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.
April 1, 1997
Date of Patent:
July 20, 1999
Micron Technology, Inc.
Mark E. Jost, David J. Hansen, Steven M. McDonald
Abstract: In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.
Abstract: First and second electrical components on an integrated circuit chip are electrically connected respectively to a wire bonding pad and to a probe contacting area of a size significantly less than the bonding pad. The pad and contacting area are electrically isolated whereby both components can be separately electrically tested by test probes contacting each of the pad and the contact area. After the components have been tested, the bonding pad and the probe contact area are electrically connected together for electrically connecting the first and second components. The electrical connection is made by bonding a terminal wire to the bonding pad as well as to an extension from the contact area substantially filling a space within the bonding pad and underlying the joint formed between the terminal wire and the bonding pad.
Abstract: A semiconductor device (400) and method are provided for multiplying a capacitance. A contact region (402) is formed in an island in a semiconductor substrate (499) bounded by an isolation region (403), producing the capacitance at the junction of the contact region (402). A dielectric layer (404) is formed over the semiconductor substrate (499) adjacent to the contact region (402). A contact layer (408) is formed over the dielectric layer (404) wherein an inversion layer (406) is formed under the contact layer (408), producing an inversion capacitance in response to an enabling signal. The inversion capacitance corresponds to a multiple of the capacitance.
Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.
Abstract: To form a plurality of patterned conductor leads in the same layer of an integrated circuit, an insulating film is etched to form a plurality of patterned grooves by plasma etching using an etching gas containing carbon and fluorine to which an additive gas containing carbon is added. The etching rate is substantially proportional to the groove width, so that the groove depth is substantially proportional to the groove width. Grooves are filled with a conductive material to form patterned conductor leads. Thus, an aspect ratio of the patterned conductor leads is kept in a certain range, resulting in an improvement in yield and reliability of the conductor leads. The conductor leads formed of material containing copper are coated with a diffusion preventive film.
Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.
January 21, 1997
Date of Patent:
April 6, 1999
Christopher K. Davis, George Bajor, James D. Beasom, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli
Abstract: There is provided a semiconductor integrated circuit chip including (a) a semiconductor substrate, (b) an insulating film formed on the semiconductor substrate, (c) first, second and third timing pulse signal lines each of which is formed of a common metal wiring layer and from which clock skew is generated, (d) an internal circuit to which the first, second and third timing pulse signal lines are electrically connected, (e) a first control signal line being designed to keep a high level while the internal circuit is in operation, and (f) a second control signal line being designed to keep a low level while the internal circuit is in operation.