Patents Examined by Mahshid Saadat
  • Patent number: 6448624
    Abstract: A semiconductor sensor chip is provided with a weight portion supported in a frame via beams whereby acceleration up to substantially ±1 G can be detected by utilizing piezoresistance effect of resistor elements formed on the beams. The semiconductor sensor chip is supported by a seat having a thermal expansion coefficient equivalent to that of the semiconductor sensor chip via the frame. The frame and the seat are adhered to each other by a flexible adhesive agent mixed with a plurality of resin beads functioning as spacers and under an adhesion state, air damping of the weight portion is carried out by setting a dimension of an air gap between the weight portion and the seat to a range of 7 through 15 &mgr;m.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: September 10, 2002
    Assignee: Denso Corporation
    Inventors: Seiichiro Ishio, Kenichi Ao, Minoru Murata, Yasuki Shimoyama, Tomohito Kunda, Norio Kitao
  • Patent number: 6300653
    Abstract: A method for forming within an integrated circuit a high areal capacitance planar capacitor, and the high areal capacitance planar capacitor which results from the method. There is first formed upon a semiconductor substrate a first planar capacitor electrode. The first planar capacitor electrode has a first planar capacitor dielectric layer formed thereupon, and the first planar capacitor dielectric layer has a second planar capacitor electrode formed thereupon. Formed then upon the semiconductor substrate is a Pre-Metal Dielectric (PMD) layer which is planarized until the surface of the second planar capacitor electrode is fully exposed. There is formed upon the second planar capacitor electrode a second planar capacitor dielectric layer. Finally, there is formed upon the second planar capacitor dielectric layer a third planar capacitor electrode.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: October 9, 2001
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Yang Pan
  • Patent number: 6294827
    Abstract: In a microwave hybrid integrated circuit a metallized recess (8) is formed on the back or face side of a board (1) of the metallization of which recess serves as a bottom plate (6) of a capacitor (5), a remaining portion (9) of the board (1) under the recess (8) serves as the dielectric of the capacitor (5), and a top plate (7) thereof is situated on the face side of the board (1) and makes part of a topological metallization pattern (2), the remaining portion of the thickness of the board (1) in the recess (8) being of 1 to 400 &mgr;m.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: September 25, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Viktor Anatolievich Iovdalsky, Eduard Volfovich Aizenberg, Vladimir Iliich Beil, Mikhail Ivanovich Lopin
  • Patent number: 6278149
    Abstract: In a DRAM-logic embedded integrated circuit in which a DRAM including trench capacitors of the deep trench structure and a logic circuit are mixedly formed in a semiconductor substrate, a plurality of capacitors of the deep trench structure are provided in the logic circuit portion. The plurality of capacitors are connected in parallel by wiring portions, whereby a plurality of capacitor blocks are formed. Between the respective capacitor blocks, there are provided fuse elements which selectively connect the respective wiring portions to each other or selectively separate them from each other to thereby vary the capacitance value of the capacitance blocks. These fuse elements are selectively cut off depending on the capacitance value of the capacitors required in view of the circuit design.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 21, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Sato, Yoshiaki Asao
  • Patent number: 6274894
    Abstract: A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides with oxide or another dielectric for protection during subsequent processing. Anisotropic etching is used to form shallow trenches in the substrate on either side of the gate conductor. The trenches are bounded by the dielectric-coated gate conductor and by dielectric isolation regions, or by an adjacent gate conductor in the case of non-isolated transistors. A selective epitaxy technique may then be used to grow a layer within each trench of a material having a bandgap lower than that of the semiconductor substrate. The lower-bandgap material is preferably grown only on the exposed semiconductor surfaces in the trenches, and not on the surrounding dielectric regions.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: August 14, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Manfred Horstmann, Frederick N. Hause
  • Patent number: 6268289
    Abstract: A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: July 31, 2001
    Assignee: Motorola Inc.
    Inventors: Rina Chowdhury, Ajay Jain, Olubunmi Adetutu
  • Patent number: 6265739
    Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: July 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Kazuhiro Shimizu, Seiichi Aritome
  • Patent number: 6265744
    Abstract: An electronic field reduction in a corner of a trench section of a semiconductor is achieved by forming a p-type base region in a source area of an n-type drain region, and both an n-type source region and a gate leading region are formed in a surface area of the p-type base region separately from each other. A trench section is formed in both the source region and gate leading region to reach the drain region. Polysilicon is formed in the trench section and on the surface of a semiconductor substrate with a gate insulation film interposed therebetween and then thermally treated. An interlayer insulation film is deposited on the entire surface of the semiconductor substrate, and then contact holes reaching the gate leading region and the source and base regions in the peripheral portion of the trench section in the source region are formed. A source/base electrode which contacts both the source and base regions through one of the contact holes is formed.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: July 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Okumura
  • Patent number: 6262467
    Abstract: A semiconductor device is disclosed, together with a fabricating method therefor. The semiconductor device has an etch barrier structure, made with SiN or SiON, which is formed on an element-isolating region alongside an active region. Although there is an alignment error which causes the element-isolating region to be exposed, the etch barrier structure protects the element-isolating region from being etched when carrying out the etching processes for contact holes in a semiconductor memory cell. Thus, while preventing the deterioration of element-isolation properties, the etch barrier structure can affords a larger allowable alignment error in the etching processes for contact holes, so it is possible to make a small active region and thus, highly integrate semiconductor devices.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: July 17, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Dae Hee Hahn
  • Patent number: 6249017
    Abstract: In a trench capacitor type semiconductor memory device including a semiconductor substrate having a trench and first and second impurity diffusion source/drain regions, a capacitor electrode buried in the trench, and a substrate-side capacitor electrode and a capacitor insulating layer within the semiconductor substrate and adjacent to a lower portion of the capacitor electrode, a buried insulating layer is formed between the semiconductor substrate and an upper portion of the capacitor electrode. The buried insulating layer is thicker than the capacitor insulating layer. However the buried insulating layer on a surface of the second impurity diffusion source/drain region is thin, or in direct contact with the capacitor electrode. A silicide layer is formed on the second impurity diffusion source/drain region and the capacitor electrode.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: June 19, 2001
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Togo
  • Patent number: 6246068
    Abstract: A method is provided for producing, with high reproducibility, an SOI substrate which is flat and high in quality, and simultaneously for achieving resources saving and reduction in cost through recycling of a substrate member. For accomplishing this, a porous-forming step is performed forming a porous Si layer on at least a surface of an Si substrate and a large porosity layer forming step is performed for forming a large porosity layer in the porous Si layer. This large porosity layer forming step is performed by implanting ions into the porous Si layer with a given projection range or by changing current density of anodization in said porous-forming step. At this time, a non-porous single-crystal Si layer is epitaxial-grown on the porous Si layer. Thereafter, the surface of the porous Si layer and a support substrate are bonded together, and then separation is performed at the porous Si layer with the large porosity. Subsequently, selective etching is performed to remove the porous Si layer.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: June 12, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Takao Yonehara, Kiyofumi Sakaguchi
  • Patent number: 6242799
    Abstract: An anisotropic stress buffer includes a plate or sheet-like body having relatively low elastic modulus. A plurality of elements, each having relatively high elastic modulus, are contained in the plate or sheet-like body, in such a manner that the buffer has a characteristic as a high elastic modulus member having a Young's modulus higher than a predetermined value with respect to a compression stress in the thickness direction and also has a characteristic as a low elastic modulus member having a Young's modulus lower than the predetermined value with respect to a tension stress in the planar direction. A semiconductor device includes such a anisotropic stress buffer to which a semiconductor chip is adhered. Electrode terminals of the chip are electrically connected to a wiring pattern formed on the anisotropic stress buffer.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: June 5, 2001
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Michio Horiuchi, Shigetsugu Muramatsu
  • Patent number: 6236107
    Abstract: A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 22, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Min Yu Chan, Siu Waf Low, Jing Sua Goh
  • Patent number: 6232247
    Abstract: In one aspect, the invention includes a method of improving uniformity of liquid deposition when a liquid is spin-coated over a non-circular substrate. The substrate is retained on a platform and spun. The circular platform includes a plurality of shaping members pivotally connected to the platform. The plurality of shaping members are biased by spinning the platform to form a platform surface with a circular periphery. In another aspect, the invention includes a substrate coating apparatus. Such apparatus comprises a non-circular substrate support configured to support a substrate with a planar surface and non-circular periphery. The apparatus further comprises a motor configured to spin the substrate support. A plurality of shaping members are pivotally connected with the substrate support and each shaping member has a curved outer side surface.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Brian F. Gordon, Paul D. Shirley
  • Patent number: 6229185
    Abstract: A CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contract region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: May 8, 2001
    Assignee: Winbond Electronics Corp.
    Inventor: Wei-Fan Chen
  • Patent number: 6218719
    Abstract: An anti-reflective coating having a composite layer of silicon nitride and silicon dioxide may be formed over the entire photosensitive region of the photodetector to minimize the amount of reflection. The composite layer comprises a silicon nitride layer and a dielectric layer contiguous to the silicon nitride layer. The anti-reflective coating may be formed in a CMOS process for fabricating the PN junction in the photodiode and CMOS devices for amplifying the photodetector signal, where the polysilicon gate layer is used as a etch stop. The P+ or N+ material in the PN junction of the photodiode has a distributed design where two portions of the region are separated by a distance in the range of Xd to 2Xd, where Xd is the one-sided junction depletion width, to enhance the electric field and to reduce the distance traveled by the carriers for enhancing bandwidth. A heavily doped region of the opposite type may be added between the two portions to further enhance the electric field.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: April 17, 2001
    Assignee: Capella Microsystems, Inc.
    Inventor: Koon Wing Tsang
  • Patent number: 6218727
    Abstract: A wafer frame for fixing and handling 200 mm wafers is produced with a significantly reduced weight as compared to a metal wafer frame, while maintaining mechanical and thermal material properties. This is accomplished by producing the wafer frame from a plastic with a glass fiber content of from 1 to 40% by weight.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: April 17, 2001
    Assignee: Infineon Technologie AG
    Inventors: Reinhold Merkl, Detlef Houdeau, Harald Lösch, Marianne Lösch
  • Patent number: 6218720
    Abstract: A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: April 17, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Dim-Lee Kwong, H. Jim Fulford, Jr.
  • Patent number: 6218677
    Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: April 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Tom P. E. Broekaert
  • Patent number: 6215167
    Abstract: A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity type as the collector region is formed spaced from the pn junction and at a dose higher than that of the collector region. A field plate overlaps the pn junction and the accelerating region. The field plate has an edge portion that extends past the accelerating region. When a voltage of a reverse direction is applied to the pn junction, an electric field becomes concentrated on the accelerating region as well as on the pn junction and on the edge portion of the field plate. This increases an electric field distribution area and thus also increases the breakdown voltage.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: April 10, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-ho Park