Patents Examined by Mamadou Diallo
  • Patent number: 10037675
    Abstract: Systems and methods of (remotely) controlling aspects of pools and spas and of modifying water contained therein are detailed. Internet-enabled access to pool and spa controllers may happen without any need for users to create firewall ports or utilize static internet protocol addresses. Certain networking devices may be configured using a USB connection or SD card, avoiding any requirement for an Ethernet cable or supplying separate power to the devices during configuration. Time-varying data may be obtained in respect of one or more installations and analyzed for various information.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 31, 2018
    Assignee: ZODIAC POOL SYSTEM, LLC
    Inventor: Dindo Uy
  • Patent number: 10026724
    Abstract: A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Gun-ho Chang
  • Patent number: 10020251
    Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsiao-Chun Lee, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 10020289
    Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kayoko Shibata
  • Patent number: 10012521
    Abstract: Apparatus and method for ultrasonic flow metering of viscous fluids. In one embodiment, an ultrasonic flow metering system includes an ultrasonic flow meter, a flow conditioner, and a reducer. The ultrasonic flow meter includes a pair of ultrasonic transducers arranged to exchange ultrasonic signals through a fluid stream flowing between the transducers. The flow conditioner is disposed upstream of the ultrasonic flow meter. The reducer is disposed between the flow conditioner and the ultrasonic flow meter to reduce the cross sectional area of the fluid stream flowing from the flow conditioner to the ultrasonic flow meter.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 3, 2018
    Assignee: Daniel Measurement and Control, Inc.
    Inventors: Paththage Jayampathi Anuradha Priyadarshana, Drew Shine Weaver, Peter Syrnyk, Dale Goodson
  • Patent number: 10014209
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Ruilong Xie, Hoon Kim, Chanro Park, Sukwon Hong
  • Patent number: 10014213
    Abstract: A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces. According to one embodiment, the metal is selected from the group consisting of ruthenium (Ru), cobalt (Co), aluminum (Al), iridium (Ir), iridium (Ir), rhodium (Rh), osmium (Os), palladium (Pd), platinum (Pt), nickel (Ni), and a combination thereof.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 3, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Kandabara N. Tapily, Robert D. Clark, Gerrit J. Leusink
  • Patent number: 9999138
    Abstract: A method of making connection elements for a microelectronic device is provided, including foil ling a conducting layer on a support on which there is at least one conducting pad located on a front face of the support opposite a back face thereof, the conducting layer including a first conducting portion in contact with at least one conducting pad, the first conducting portion extending on the front face and being connected to at least one second conducting portion extending in contact with at least one given wall of the support being located between the front and back faces and forming a non-zero angle with the front face; thinning the support at the back face to release one conducting end of the second conducting portion as a free conducting end projecting from the back face; and after the thinning, bending the free conducting end projecting from the back face.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 12, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Stephan Borel
  • Patent number: 9993301
    Abstract: A method for monitoring a reprocessing device for endoscopes the method including: logging one or more process parameters as well as a time of each reprocessing operation over a plurality of reprocessing operations for at least one endoscope in at least one reprocessing device; storing the logged one or more process parameters in association with the respective reprocessing operation, and performing a trend analysis of at least one logged process parameter in an evaluation device via the one or more logged process parameters.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 12, 2018
    Assignee: OLYMPUS WINTER & IBE GMBH
    Inventors: Torben Carlson, Henning Thate
  • Patent number: 9989404
    Abstract: A portable terminal includes: an acceleration measuring unit that measures acceleration of the portable terminal; a calculating unit that calculates a first feature value for in-plane directions in which the portable terminal is in contact with an object and a second feature value for an out-of-plane direction on the basis on the acceleration measured by the acceleration measuring unit in a state in which the portable terminal is put on the object, when the portable terminal is vibrated; and a specifying unit that specifies a material of the object on the basis of the first feature value and the second feature value.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 5, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Shinya Yamazaki, Toru Fuse
  • Patent number: 9991362
    Abstract: In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron containing gas and a dilute gas, and a tungsten layer is formed on the seed layer by supplying a tungsten containing gas. A flow ratio of a flow amount of the boron containing gas to a total flow amount of the boron containing gas and the dilute gas is in a range from 1/21 to 1/4.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu
  • Patent number: 9985213
    Abstract: A compound is represented by a formula (1) below. In the formula (1), n is 1 or 2. Ar1 is represented by a formula (2) below. Ar2 represents a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 carbon atoms, or a substituted or unsubstituted heterocyclic group having 1 to 20 ring atoms. Ar3 is represented by a formula (3) below.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 29, 2018
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Hirokatsu Ito, Tomohiro Nagao
  • Patent number: 9978620
    Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 22, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Gary E. Dickerson, Seng (victor) Keong Lim, Samer Banna, Gregory Kirk, Mehdi Vaez-Iravani
  • Patent number: 9975766
    Abstract: An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is more precise, and the uniformity and the homogeneity of the formed support beam are better.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 22, 2018
    Assignee: CSMC TECHNOLOGIES FABI CO., LTD.
    Inventors: Yonggang Hu, Guoping Zhou
  • Patent number: 9975761
    Abstract: A method of manufacturing a plurality of through-holes in a layer of first material, for example for the manufacturing of a probe comprising a tip containing a channel. To manufacture the through-holes in a batch process, a layer of first material is deposited on a wafer comprising a plurality of pits a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits; using the second layer as a shadow mask when depositing a third layer at an angle, covering a part of the first material with said third material at the central locations, and etching the exposed parts of the first layer using the third layer as a protective layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 22, 2018
    Assignee: SmartTip BV
    Inventor: Edin Sarajlic
  • Patent number: 9972690
    Abstract: A substrate includes a trench with walls and a base. The substrate also includes a dielectric field plate. The dielectric field plate consists of at least one first dielectric layer, which only adjoins lower sections of the walls of the trench and the base of the trench. Parasitic capacitances can be reduced when using this substrate for power transistors.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 15, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Achim Trautmann, Christian Tobias Banzhaf
  • Patent number: 9964590
    Abstract: Configurable probe blocks for system monitoring are disclosed. Example methods disclosed herein to monitor a system include configuring a probe block based on a first value of a control word specifying that a first probe input from a set of available probe inputs associated with the probe block is to be enabled and that a first trigger condition from a set of available trigger conditions associated with the probe block is to be assigned to the first probe input. Some such disclosed example methods also include processing, in accordance with the configuring of the probe block based on the first value of the control word, monitored data accessible via the probe block to determine probe data to output from the probe block.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 8, 2018
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Mostafa Tofighbakhsh, Thomas A. Anschutz
  • Patent number: 9966323
    Abstract: A semiconductor device includes an electronic component connected to a component pad of a wiring substrate, a connection member connected to a connection pad of the wiring substrate, and an encapsulation resin that encapsulates the electronic component and connection member. A wiring unit includes a first pad, embedded in the encapsulation resin, and a second pad, formed integrally with the first pad from the same metal. The second pad includes an external device connection surface located at a higher position than an upper surface of the encapsulation resin. A reinforcement plate includes a base, embedded in the encapsulation resin, and a heat dissipation portion, formed integrally with the base from the same metal. The first pad and the base each include a curved side surface that widens outwardly toward the upper surface of the encapsulation resin.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 8, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Hitomi Imai
  • Patent number: 9966335
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 8, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9966519
    Abstract: Techniques are provided for forming a gallium nitride flip-chip light-emitting diode. In an aspect, a device is provided that includes a gallium nitride layer, a passivation layer, a set of first conductive layers, and a second conductive layer. The gallium nitride layer is formed on a substrate that includes a first plurality of recesses associated with a first structure and a second plurality of recesses associated with a second structure, where the first plurality of recesses and the second plurality of recesses are associated with a first conductive material. The set of first conductive layers is formed on the passivation layer and corresponds to the first conductive material. The second conductive layer is formed on the passivation layer and corresponds to a second conductive material.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 8, 2018
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kei May Lau, Wing Cheung Chong