Patents Examined by Mamadou L Diallo
  • Patent number: 11075127
    Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 27, 2021
    Assignee: Lam Research Corporation
    Inventors: Seshasayee Varadarajan, Aaron R. Fellis, Andrew John McKerrow, James Samuel Sims, Ramesh Chandrasekharan, Jon Henri
  • Patent number: 11069632
    Abstract: The present disclosure provides an array substrate. The array substrate includes a plurality of shielding layers disposed on a glass substrate and arranged at intervals; a dielectric layer spread on the glass substrate and covering the shielding layers, wherein the dielectric layer includes a plurality of dielectric patterns, the dielectric patterns include main dielectric patterns and auxiliary dielectric patterns disposed on at least one side of the main dielectric patterns; and a gate insulating layer disposed on the dielectric layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 20, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chao He
  • Patent number: 11063012
    Abstract: The present disclosure provides a semiconductor structure having an organic dielectric layer disposed under a bump pad and configured for stress relief, and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a first dielectric layer disposed on the first surface of the substrate; a second dielectric layer disposed on the second surface of the substrate; a conductive via extending through the substrate and partially through the first dielectric layer and the second dielectric layer; a third dielectric layer disposed within the second dielectric layer and surrounding a portion of the conductive via; and a bump pad disposed over the third dielectric layer and the conductive via, wherein a dielectric constant of the third dielectric layer is substantially different from a dielectric constant of the second dielectric layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11062947
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Patent number: 11061135
    Abstract: A method for detecting a buried non-conductive pipe includes transmitting, by a radio frequency (RF) transmitter, guided RF energy through one end of the non-conductive pipe, receiving, by a RF receiver, electromagnetic signals due to RF energy leaks in one or more locations along the non-conductive pipe, and processing, by one or more processors, the received signals to determine a location of the non-conductive pipe. A system for detecting a buried non-conductive pipe includes a RF transmitter configured to transmit guided RF energy through one end of the non-conductive pipe, a RF receiver configured to receive electromagnetic signals due to RF energy leaks in one or more locations along the non-conductive pipe, and one or more processors configured to process the received signals to determine a location of the non-conductive pipe.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 13, 2021
    Assignee: Heath Consultants Incorporated
    Inventors: Ben Allen Abbott, Donald R. Poole
  • Patent number: 11056410
    Abstract: A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Shiro Hara, Sommawan Khumpuang, Fumito Imura
  • Patent number: 11054500
    Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 6, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Samala Sreekiran, Krishnanshu Dandu, Ross Kulak
  • Patent number: 11049873
    Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 29, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Chenming Hu, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11049827
    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minjung Choi, Sooho Shin, Yeonjin Lee, Junghoon Han
  • Patent number: 11049770
    Abstract: Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 29, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Suketu A. Parikh
  • Patent number: 11049791
    Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Jimin Yao, Veronica Strong
  • Patent number: 11043551
    Abstract: A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Juncheol Shin, Jeongho Lee, Hokyoon Kwon, Yanghee Kim
  • Patent number: 11043736
    Abstract: An antenna beam tracking system has dynamic interference reduction. The system includes antennas that can form multiple beams, each beam of which can continually track or point its beams independently in various angular directions. A first beam continually tracks and receives (downlink) signals from a desired source or node such as a satellite or terrestrial node which generally has an apparent motion relative to the antenna. A second beam continually tracks and receives potentially harmful interference signals that may arise from different directions. The signals of the second beam are dynamically coupled to the signals in the first beam in such a manner as to effect cancellation or substantial reduction of the interference.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 22, 2021
    Assignee: Isotropic Systems, Ltd.
    Inventors: Daniel F. Difonzo, Jeremiah P. Turpin
  • Patent number: 11038147
    Abstract: The present disclosure relates to an organic electroluminescence device with enhanced out-coupling efficiency. The electroluminescence device comprises a substrate, a first electrode disposed on the substrate, an organic layer and a second electrode. The organic layer is formed between the first electrode and the second electrode. The organic layer comprises one or more nanoparticles forming protrusion features on the organic layer thereby forming a topographical structured organic layer in the electroluminescence device. The electroluminescence device is capable of reducing the surface plasmon polariton loss thereby, enhancing the light out-coupling the electroluminescence device.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 15, 2021
    Assignee: Sumitomo Chemical Company Limited
    Inventors: Philip Benzie, Mark Herrington, Karen Alsop-Fox
  • Patent number: 11037915
    Abstract: An IC chip comprises LED devices exposed on a front side of the IC chip, I/O bumps on a back side of the IC chip, a first die forming a stack with the LED devices and comprising driver circuits electrically connected to the LED devices, a first circuit that extends along the vertical direction from the front side of the IC chip towards a back side of the IC chip and across at least a thickness of the first die to provide electrical connections between the LED devices and at least some of the I/O bumps, a second die including pipelining circuits and control circuits for the driver circuits, a second circuit that extends from the second die, and a circuit board electrically connected to the I/O bumps and to a power system.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 15, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 11038037
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 11038091
    Abstract: Light-emitting device packages include a package substrate surrounded by a lower molding member, a light-emitting device on the package substrate and surrounded by an upper molding member, a heat conductive pad between a lower surface of the light-emitting device and an upper surface of the package substrate, a first electrode on an upper surface of the light-emitting device, a second electrode on the upper surface of the light-emitting device, a fluorescent material on the upper surface of the light-emitting device, and a plurality of bonding wires electrically connecting the package substrate with separate, respective electrodes of the first electrode and the second electrode.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Youngjeong Yoon
  • Patent number: 11029661
    Abstract: Embodiments disclosed herein provide systems, methods, and computer-readable media to remotely actuate a user interface of a computing device. In a particular embodiment, a method includes receiving actuation information for a targeted portion of the user interface and determining control signals for a piezoelectric grid. The control signals direct application of electricity to the piezoelectric grid to deform the piezoelectric grid for actuation of the targeted portion of the user interface. The method further includes transferring the control signals to the piezoelectric grid.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 8, 2021
    Assignee: Avaya Inc.
    Inventor: Shahid Mahmood
  • Patent number: 11031378
    Abstract: A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Zengyu Zhou
  • Patent number: 11022678
    Abstract: Radio frequency motion sensors may be configured for operation in a common vicinity so as to reduce interference. In some versions, interference may be reduced by timing and/or frequency synchronization. In some versions, a master radio frequency motion sensor may transmit a first radio frequency (RF) signal. A slave radio frequency motion sensor may determine a second radio frequency signal which minimizes interference with the first RF frequency. In some versions, interference may be reduced with additional transmission adjustments such as pulse width reduction or frequency and/or timing dithering differences. In some versions, apparatus may be configured with multiple sensors in a configuration to emit the radio frequency signals in different directions to mitigate interference between emitted pulses from the radio frequency motion sensors.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 1, 2021
    Inventors: Stephen McMahon, Przemyslaw Szkot, Redmond Shouldice