Patents Examined by Marc-Anthony Armand
  • Patent number: 10978527
    Abstract: A display substrate includes a base substrate provided thereon with a pixel defining layer and a plurality of organic light emitting diodes, a plurality of conductive structures are provided on a side of a top electrode layer away from the base substrate, the top electrode layer being on the pixel defining layer, an orthographic projection of the conductive structures on a plane where the pixel defining layer is within an area where the pixel defining layer is disposed, the conductive structures are coupled to a portion of the top electrode layer on the pixel defining layer, the remaining portion of the top electrode layer is provided with a planarization layer on a side of the top electrode layer away from the base substrate, and an auxiliary electrode is on a side of the planarization layer away from the base substrate, and is coupled to the conductive structures.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 13, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chengyuan Luo
  • Patent number: 10978663
    Abstract: The present disclosure relates to an electroluminescence lighting device. The present disclosure provides an electroluminescence light device comprising: a substrate including an emission area divided into a plurality of segments and non-emission area surrounding the emission area; a segment line arranged from the non-emission area to the segment; a buffer layer on the segment line; an auxiliary line defining a plurality of pixels within each segment on the buffer layer; a first pad disposed at the non-emission area; a segment switch disposed at the non-emission area and connecting the first pad to the segment line; and an emission element disposed at each pixel.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 13, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Youngkyun Moon, JongMin Kim, Seunghyun Youk
  • Patent number: 10971621
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and first and second control electrodes. The first and second electrodes are provided on the semiconductor body. The first and second control electrodes each include a first portion positioned between the semiconductor body and the first electrode, a second portion positioned between the semiconductor body and the second electrode, and a third portion linked to the first and second portions. The semiconductor body includes first to fourth semiconductor layers. The second semiconductor layer is provided on the first semiconductor layer, and extends along the first to third portions. The fourth semiconductor layer is provided selectively on the second semiconductor layer, and extends along the second and third portions. The fourth semiconductor layer includes second conductivity-type impurities with a higher concentration than a concentration of second conductivity-type impurities in the second semiconductor layer.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 6, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Kohei Oasa, Toshifumi Nishiguchi
  • Patent number: 10971175
    Abstract: A storage element is provided. The storage element includes a memory layer; a fixed magnetization layer; an intermediate layer including a non-magnetic material; wherein the intermediate layer is provided between the memory layer and the fixed magnetization layer; wherein the fixed magnetization layer includes at least a first magnetic layer, a second magnetic layer, and a non-magnetic layer, and wherein the first magnetic layer includes a CoFeB composition. A memory apparatus and a magnetic head are also provided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 6, 2021
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Hiroyuki Uchida
  • Patent number: 10971591
    Abstract: Provided is a power semiconductor device that prevents element breakage, thus improving its reliability. The power semiconductor device includes a first main electrode. The first main electrode includes a first metal film, an intermediate film, and a second metal film. The first and second metal films are made of metal having an Al concentration greater than or equal to 95 wt %. The intermediate film contains primary-constituent phases each formed of a metal compound, and contains a secondary-constituent phase formed of an iron group element. The metal compound is that of at least one kind of element selected from a group consisting of a group 4A element, a group 5A element, and a group 6A element, and at least one kind of element selected from a group consisting of C and N. The intermediate film has a higher degree of hardness than the second metal film.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 6, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Dai Kitano
  • Patent number: 10957641
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masahiro Inohara
  • Patent number: 10948589
    Abstract: SAR imaging may be performed using a short-pulse laser to generate range-resolved reflection data. A short-pulse laser may be advantageous over other techniques to acquire the range-resolved data, especially in cases with very distant targets or other cases with low signal-to-noise ratio information, because a short-pulse laser can determine the range to individual reflectors with a single photon return and is more adaptable to a photon-starved inversion algorithm. This technique can be used with both mono-static and bi-static SAR configurations.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 16, 2021
    Inventors: Bruce Carlsten, David Thompson, David Palmer
  • Patent number: 10950775
    Abstract: The present invention provides a conversion material including a first phase providing a matrix and a second phase comprising a nanoscale or microscale material providing electron mobility. The conversion material converts heat from a single macroscopic reservoir into voltage.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: March 16, 2021
    Inventors: Gerold Kotman, Niklas Kotman, Riccardo Raccis
  • Patent number: 10950544
    Abstract: A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ik Lee, Dai Hong Kim, Ji Woon Im, Se Mee Jang, Bo Ra Nam
  • Patent number: 10943831
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10937809
    Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Seung-Yeul Yang, Fei Zhou, Adarsh Rajashekhar
  • Patent number: 10935663
    Abstract: Disclosed are a system, apparatus, and method for monitoring integrity of satellites, and global navigation satellite systems (GNSS). One or more satellites in one or more GNSS are monitored based on a reference crowdsourced integrity report. One or more satellite integrity metrics are determined for the one or more satellites based at least on signals from the one or more satellites. A position of the mobile device is estimated. The position of the mobile device and the one or more satellite integrity metrics are provided.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 2, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Zoltan Biacs, Ning Luo
  • Patent number: 10930774
    Abstract: A trench MOSFET is disclosed having shielded trenched gates in active area, multiple floating trenched gates and at least one channel stop trenched gate in termination area. A semiconductor power device layout is disclosed consisting of at least two said trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line, making the invented trench MOSFET be feasibly achieved without degraded performance.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 23, 2021
    Assignee: NAMI MOS CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 10930672
    Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Siyeon Cho, Hyeri Shin, Sung-Bok Lee, Yusik Choi, Sungyung Hwang
  • Patent number: 10930893
    Abstract: The present disclosure discloses an organic light-emitting diode device, a manufacturing method thereof and a display device. The organic light-emitting diode device comprises: a substrate (100); an organic light-emitting diode layer (200) on a side of the substrate (100); and a barrier layer (510) configured to block ultraviolet rays from entering the organic light-emitting diode layer, wherein the barrier layer is on a side of the organic light-emitting diode layer away from the substrate or on a side of the organic light-emitting diode layer close to the substrate. The organic light-emitting diode device can solve the technical problem of short service life due to the influence of ultraviolet rays in the sunlight.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 23, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Guanyin Wen, Lei Chen, Haidong Wu, Na Li
  • Patent number: 10921866
    Abstract: Techniques and devices for access to high frame-rate radar data via a circular buffer are described. In some implementations, a radar sensor collects radar data regarding objects detected by a radar field and stores the data to a circular buffer. A data manager monitors the circular buffer and processes data requests from multiple applications. Through use of the described techniques and devices, the multiple applications can efficiently access the requested radar frame data from the circular buffer, reducing both memory requirements and processor resource usage associated with providing the requested data.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 16, 2021
    Assignee: Google LLC
    Inventors: Jason P. Sanders, Gabriel O. Taubman
  • Patent number: 10914829
    Abstract: A positioning sensor includes m receiving antennas connected to a feeder circuit and n variable loads, and a receiver that receives a first signal via the m receiving antennas. The positioning sensor further includes a memory that stores a first signal strength value of a first signal that the receiver receives when a variable load varies in value, and a processor that calculates a second signal strength value from a complex propagation channel, searches for a complex propagation channel candidate that has a minimum difference between a first signal strength and a second signal strength, determines the complex propagation channel candidate to be a complex propagation channel when the receiver receives the first signal, and estimates an incoming direction of the first signal from the determined complex propagation channel.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 9, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Nakayama, Shoichi Iizuka, Naoki Honma
  • Patent number: 10910711
    Abstract: Systems, methods, and computer-readable media for receiver channel calibration are provided. The method includes generating a plurality of calibration signals corresponding to a plurality of receiver channels, respectively. The plurality of calibration signals are combined with a plurality of data signals, respectively, thereby generating a plurality of combined signals. The plurality of combined signals are propagated through at least portions of the plurality of receiver channels, respectively. The plurality of calibration signals are extracted from the propagated plurality of combined signals, respectively. At least two signal characteristics of at least two of the extracted plurality of calibration signals are compared. At least one adjustment in gain, phase, or timing for at least one of the receiver channels is identified based on a result of the comparing. Based on the identified adjustment, a data signal received via the at least one of the plurality of receiver channels is adjusted.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 2, 2021
    Assignee: Loon LLC
    Inventors: Sharath Ananth, Pascal Stang
  • Patent number: 10910555
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating three magnetic free layers separated by two perpendicular enhancement layers (PELs) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a third perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 2, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Xiaojie Hao, Longqian Hu, Yiming Huai
  • Patent number: 10910396
    Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junhyoung Kim, Geunwon Lim, Kwang-soo Kim