Patents Examined by Marc-Anthony Armand
  • Patent number: 10615495
    Abstract: Technologies pertaining to the calibration of ultra-wide-band active-electronically-scanned arrays to compensate for transmit and receive mutual coupling between array elements and/or non-ideal isolated channels are described herein. A plurality of near-field measurements are taken by way of probe or probes that may be moved among a plurality of positions aligned with respective elements in the array. For each position of the probe, each of the elements of the array is stimulated to transmit or receive a calibration signal to or from the probe, respectively. Frequency-domain transfer functions are computed from the received signals by the probe or the element for each of the array elements in each of the positions of the probe. The inverse of the matrix of transfer functions comprise frequency-domain transmit and receive correction factors that are used to modify desired array inputs/outputs such that the modified signals correct for mutual coupling between elements in the array.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 7, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Hung Loui
  • Patent number: 10613196
    Abstract: The present embodiments relate to a radar signal processing apparatus and a signal processing method thereof in which an additional beamforming is performed by reflecting an angle of a target that is positioned in front of the vehicle or by reflecting a surrounding clutter situation thereof in order to thereby improve the performance of detecting the target in front of the vehicle.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 7, 2020
    Assignee: MANDO CORPORATION
    Inventor: HaeSueng Lim
  • Patent number: 10615115
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masahiro Inohara
  • Patent number: 10615053
    Abstract: Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erma Gallenero Gardose, Liya Flores Aquino
  • Patent number: 10611630
    Abstract: In various embodiments, a method of processing a monocrystalline substrate is provided. The method may include severing the substrate along a main processing side into at least two monocrystalline substrate segments, and forming a micromechanical structure comprising at least one monocrystalline substrate segment of the at least two substrate segments.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 7, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 10602282
    Abstract: A hearing aid includes a signal processor, a input transducer electrically connected to the signal processor, a receiver electrically connected to the signal processor, an adaptive feedback cancellation filter configured to suppress feedback from a signal path between the receiver and the input transducer, and a feedback gain correction unit configured for adjusting a gain parameter of the signal processor based at least in part on coefficients of the adaptive feedback cancellation filter. A method of adjusting a gain parameter of a signal processor of a hearing aid includes monitoring filter coefficients of a feedback cancellation filter of the hearing aid, and adjusting the gain parameter of the signal processor in dependence of the monitored filter coefficients.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: March 24, 2020
    Assignee: GN Resound A/S
    Inventor: Erik Cornelis Diederik Van Der Werf
  • Patent number: 10586777
    Abstract: To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kentaro Yamada, Shigeki Tomaru, Taketoshi Fukushima
  • Patent number: 10580773
    Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 3, 2020
    Assignee: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
  • Patent number: 10573584
    Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 25, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Kimura, Takeshi Sunaga, Shouji Yasunaga, Akihiro Koga
  • Patent number: 10564270
    Abstract: A method for calibrating sensors devices mounted on a machine is disclosed. The method includes transforming a first 3D point cloud to generate a transformed first 3D point cloud based on an alignment of the first 3D point cloud with a 3D model of the machine. The first 3D point cloud includes 3D point cloud of one or more features of a terrain around the machine, and the machine. The method further includes aligning a second 3D point cloud with the transformed first 3D point cloud based on the one or more features of the terrain, to determine one or more transformation parameters. Thereafter, one or more calibration parameters for the second sensor device is extracted from the one or more transformation parameters. The second sensor device is calibrated based on the one or more calibration parameters.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: February 18, 2020
    Assignee: Caterpillar Inc.
    Inventors: Qi Wang, Paul Edmund Rybski
  • Patent number: 10559586
    Abstract: A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Taichi Iwasaki, Takeshi Sonehara, Hiroyuki Nitta
  • Patent number: 10553733
    Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Huang, Chien Nan Tu, Chi-Yuan Wen, Ming-Chi Wu, Yu-Lung Yeh, Hsin-Yi Kuo
  • Patent number: 10553550
    Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: February 4, 2020
    Assignee: Sony Corporation
    Inventors: Yoshikazu Motoyama, Hiroki Tsunemi, Hideo Yamagata
  • Patent number: 10552761
    Abstract: Technologies for performing non-intrusive fine-grained power monitoring of a datacenter are provided. Hardware component state information for servers in the datacenter is collected, along with aggregate power consumption measurements for the datacenter. The servers are grouped into multiple virtual homogenous server clusters (VHCs) based on characteristics of the servers. A power model is constructed comprising multiple power mapping functions associated with the multiple VHCs. Component state information of a particular server can then be analyzed, along with a corresponding aggregate power consumption measurement, using the constructed power model to determine an approximate power consumption of the particular server. The approximate power consumption of the server can then be displayed and/or provided to one or more power management applications.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 4, 2020
    Assignee: UVic Industry Partnerships Inc.
    Inventors: Guoming Tang, Kui Wu, Fangming Liu
  • Patent number: 10553805
    Abstract: An organic EL display panel with improved visibility is disclosed which includes sub-pixels each emitting light of a color selected from R, G, and B and disposed in a matrix, pixel electrodes disposed above a substrate in the matrix corresponding to the sub-pixels, and column banks row-directionally arranged extending in the column direction. The organic EL display panel further includes pairs of auxiliary column banks extending parallel to the main column banks, disposed in gaps between pairs of the column banks adjacent to each other where the pixel electrodes corresponding to the sub-pixels emitting the B color are present, each pair of the auxiliary column banks covering both edges in the row direction of each of the pixel electrodes therebetween.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 4, 2020
    Assignee: JOLED INC.
    Inventors: Noriteru Maeda, Kenichi Nendai
  • Patent number: 10546940
    Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 10541314
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, forming a plurality of doped regions in the base substrate, forming an initial capping layer covering surfaces of the plurality of doped regions, forming a dielectric layer on the initial capping layer and the base substrate, forming a plurality of vias in the dielectric layer to expose a surface portion of the initial capping layer, and etching the exposed surface portion of the initial capping layer at a bottom of each via to form a silicide region exposed at the bottom of the via. The silicide region has a reduced thickness compared with a thickness of the initial capping layer. The method further includes forming a metal silicide layer by performing a self-aligned silicide process on an entire silicide region. The metal silicide layer is in contact with the plurality of doped regions.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10535610
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chia-Liang Liao, Yu-Cheng Tung, Chien-Hao Chen, Chia-Hung Wang
  • Patent number: 10529713
    Abstract: A method of forming fin field effect devices is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a dielectric pillar on the substrate between two adjacent vertical fins, wherein at least one of the vertical fins is on a first region of the substrate, and at least one of the vertical fins is on a second region of the substrate. The method further includes growing a bottom source/drain layer on the first region of the substrate and the second region of the substrate. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, and a filler layer on the bottom spacer layer. The method further includes forming a cover block on the first region of the substrate, and removing the portion of the filler layer on the second region of the substrate.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Kangguo Cheng, Wenyu Xu, Chen Zhang
  • Patent number: 10527414
    Abstract: The technology relates to a system and method for monitoring an environment. The method comprises receiving first and second sets of data from a plurality of mobile units, wherein the first set of data is associated with a first temporal indicator, the second set of data is associated with a second temporal indicator and each mobile unit comprises: a position determining device configured to generate position data associated with a position of the mobile unit within the environment, and a laser scanning device configured to generate scan data based on a scan of at least part of the environment; determining a first parameter associated with the first set of data; determining a second parameter corresponding to the first parameter and associated with the second set of data; and determining a difference between the first and second parameters.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 7, 2020
    Assignee: 3D LASER MAPPING LIMITED
    Inventor: Graham Hunter