Abstract: A multiple input multiple output (MIMO) radar sensor encodes or decodes radar signals generated by multiple MIMO transmitters using a mixture of sub-set digital codes that discriminate between different sub-sets of MIMO transmitters and Doppler-division codes that discriminate between different MIMO transmitters within each of the sub-sets.

Abstract: The invention relates to a method of producing a plate arrangement comprising two plates (1, 2) which, at least in sections, have an intermediate space (4) located between them and a constant distance (d) to one another and/or are arranged parallel to one another and between which a fusible solder material (3, 3?) is arranged. The task of setting a defined distance between the plates as accurately as possible is solved according to the invention by creating a pressure difference between the intermediate space (4) between the plates and the outer space surrounding the plates in such a way that the pressure in the outer space is higher than in the intermediate space (4) and that the temperature of the solder material (3, 3?) is at least temporarily raised above its melting temperature during the existence of the pressure difference.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.

Abstract: A processing apparatus includes a controller configured to control an operation of forming condensing points in a processing target object. In forming the condensing points by radiating a laser light to an inside of the processing target object periodically from a modifying device while rotating the processing target object held by a holder relative to the modifying device by a rotating mechanism and, also, by moving the modifying device in a diametrical direction relative to the holder by a moving mechanism, the controller controls a number and an arrangement of the condensing points, which are simultaneously formed at different positions in a plane direction of the processing target object, based on a relative rotation number of the processing target object and a radiation pitch of the laser light.

Abstract: Vapor deposition processes are provided for bottom up filling of trenches and other structures with metal nitrides such as vanadium nitride and titanium nitride. In some embodiments, VCl4 can be used as an etchant source in the deposition processes. The reaction conditions are selected such that some Cl2 forms in the reaction space and preferentially etches deposited metal nitride at the upper surfaces of a trench or other three-dimensional feature on a substrate. The self-etching during the deposition process facilitates a bottom up filling of the feature and may reduce or eliminate the formation of seams or voids.

Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.

Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

Abstract: Semiconductor device A1 includes: semiconductor element 1 turning on and off connection between drain electrode 11 and source electrode 12; semiconductor element 2 turning on and off connection between drain electrode 21 and source electrode 22; metal component 31 with semiconductor element 1 mounted; metal component 32 with semiconductor element 2 mounted; and conductive substrate 4 including wiring layers 411, 412 with insulating layer 421 between them. Wiring layer 411 includes power terminal section 401 connected to drain electrode 11. Wiring layer 412 includes power terminal section 402 connected to source electrode 22. Power terminal sections 401, 402 and insulating layer 421 overlap with each other as viewed in z direction. Conductive substrate 4 surrounds semiconductor elements 1, 2 as viewed in z direction, while overlapping with a portion between metal components 31, 32 as viewed in z direction.

Abstract: An integrated circuit lead frame and a semiconductor device thereof are provided. The integrated circuit lead frame includes a die pad and a plurality of leads. The die pad is provided to attach a die. The plurality of leads are provided for connection to the die through wire bonding. The leads include a pair of a first lead and a second lead. The first lead includes a first body and a first extension portion connected to the first body. The second lead includes a second body and a second extension portion connected to the second body. The first extension portion and the second extension portion extend in directions toward each other.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A semiconductor device includes a resin member, a die pad including a first surface on which a semiconductor chip is disposed and covered by the resin member, and a second surface opposite to the first surface and partially covered by the resin member such that a first portion of the second surface is exposed from the resin member, and a plurality of electrodes each separated from the die pad and including a first surface connected to the semiconductor chip and covered by the resin member, and a second surface partially covered by the resin member such that a second portion of the second surface is exposed from the resin member. The first portion of the die pad includes at least four sides, each of which is nonparallel to a side of the second portion of one of the electrodes that faces the side.

Abstract: The disclosure provides a micro light-emitting diode mass transfer apparatus and method. The micro light-emitting diode mass transfer apparatus includes a solution container, display backplanes, a solution drive assembly and a liquid level control assembly. The solution container contains a transfer solution, and micro light-emitting diodes to be transferred float on the liquid surface of the transfer solution. The display backplanes are submerged in the transfer solution and each provided with a plurality of chip mounting cells; mounting cell opening directions of the plurality of chip mounting cells face toward the micro light-emitting diodes; and at least one of the chip mounting cells is exposed on the liquid surface. The solution drive assembly is disposed in the solution container. The liquid level control assembly is configured to control a liquid level of the transfer solution in the solution container.

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

Abstract: A semiconductor device includes an insulating substrate, wiring layers, heat dissipation layers, a semiconductor element, and a sealing resin. The wiring layers each have a first obverse face and a first reverse face oriented in opposite directions in a thickness direction of the substrate. The first reverse faces of the wiring layers are connected to the substrate. The heat dissipation layers each have a second obverse face oriented in the same direction as the first obverse face, and a second reverse face oriented opposite to the second obverse face in the thickness direction. The heat dissipation layers are located opposite to the plurality of wiring layers in the thickness direction with respect to the substrate. The second obverse faces of the heat dissipation layers are connected to the substrate. The semiconductor element is connected to one of the first obverse faces of the wiring layers. The sealing resin covers the substrate, the wiring layers, and the semiconductor element.

Abstract: Embodiments disclose methods of transferring selected microdevices on a receiver substrate. In one embodiment, a high resolution display comprising a light emitting device (LED) array may be provided to assist in transferring the microdevices. The LED array can selectively either release a layer by using light or cure a bonding layer. The pixels in the display can be turned on corresponding to a set of selected microdevices with predefined intensities to release the set of selected microdevices from the donor substrate.

Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.

Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.

Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.

Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.