Abstract: A semiconductor device includes a first semiconductor chip including an output electrode portion on a front surface thereof, the output electrode portion including a plurality of electrode regions, each of which is provided at a respective position of the output electrode portion, and a plurality of wires, each electrode region being connected to a different one or more wires among the plurality of wires, through which a respective amount of output current is output. A total number of the different one or more wires connected to each electrode region is set depending on the respective position of the electrode region of the output electrode portion, so that the electrode region has a respective current amount per wire that is equal to or less than a respective predetermined value.

Abstract: A power semiconductor device includes a first submodule including a first power semiconductor element, a second submodule including a second power semiconductor element, a positive electrode side conductor portion and a negative electrode side conductor portion, an intermediate substrate that forms a negative electrode side facing portion facing the negative electrode side conductor portion with the first submodule sandwiched between them and a positive electrode side facing portion facing the positive electrode side conductor portion with the second submodule sandwiched between them, and a plurality of signal terminals that transmit a signal for controlling the first power semiconductor element or the second power semiconductor element.

Abstract: A circuit includes input terminals adapted to be coupled to a battery; a ground terminal; and an electrostatic discharge (ESD) protection circuit coupled to the input terminals. The ESD protection circuit includes: a switch coupled between the ground terminal and the input terminals; and a control circuit coupled to the input terminals and to the switch. The control circuit is configured to: detect an ESD event at one of the input terminals; detect a transient voltage at one of the input terminals, in which the transient voltage is caused by an initial coupling of that input terminal to the battery; detect a condition in which the switch has been closed for longer than a threshold amount of time; close the switch responsive to the detected ESD event; and open the switch responsive to the detected transient voltage or the detected condition.

Abstract: A manufacturing method of a semiconductor device according to the technology disclosed in the present specification includes: providing at least one semiconductor element; connecting, to the semiconductor element, a plurality of first terminals and at least one second terminal that is a control terminal to which a voltage lower than that of the first terminal is applied; and forming a first bent part in the first terminal, in which the first bent part does not protrude on the surfaces, facing each other, of the plurality of first terminals that are adjacent to each other.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 1019 cm?3.

Abstract: A polarimetric radar consisting of a transmission arrangement, in which the carrier signals have a circular polarization, wherein all the transmitters of the transmission arrangement are used simultaneously and each transmitter is operated by way of a transmission signal, which is modulated by way of an individual digital phase code, a receiver arrangement, which receives the reflected signals via an antenna arrangement, wherein there are both reception antennas that are configured for left-hand circularly polarized electromagnetic waves and reception antennas that are configured for right-hand circularly polarized electromagnetic waves, wherein the use of a plurality of transmitters and receivers provides an overall arrangement, which is operated in accordance with the multiple-input multiple-output method.

Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.

Abstract: An apparatus comprises a ground plane (2), an integrated circuit chip (1) disposed on the ground plane (2), the integrated circuit chip (1) comprising one or more electrically conductive layers (10) encircling a periphery of the integrated circuit chip (1), and a plurality of bondwires (9) electrically coupling the one or more electrically conductive layers (10) to the ground plane (2).

Abstract: An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad.

Abstract: An ultra wide band (UWB) based radar system and method uses reflected UWB signal pulses to locate and/or track objects having a detectable radar cross-section. The system and method use the same types of UWB transceivers used to track active RF tags and includes a method of processing channel impulse response data allowing the detection, location, and tracking of non-tagged objects within a monitored area.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Abstract: A semiconductor device includes: a single die pad made of a metal or metal alloy and having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view; a signal lead arranged between the ground leads; a plurality of leads arranged around the die pad in plan view; a semiconductor chip mounted on the second surface; bonding wires connecting a signal pad of the chip and the signal lead and connecting a ground pad of the chip and the ground leads; and a mold resin covering the die pad, the signal lead, the plurality of leads, the chip, and the bonding wires; wherein an interval between the signal lead and each of the ground leads is narrower than an interval between the plurality of leads.

Abstract: A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Abstract: A sensor for motion or gesture sensing may be configured to emit radio frequency signals such as for pulsed range gated sensing. The sensor may include a radio frequency transmitter configured to emit the pulses and a receiver configured to receive reflected ones of the emitted radio frequency signals. The received pulses may be processed by a motion channel and/or a gesture channel. The gesture channel may produce signals for further processing for identification of one or more different motion gestures such as by calculating and evaluating features from any of the amplitude, phase and frequency of the output signals of the gesture channel. The sensing apparatus may optionally serve as a monitor for evaluating user activities, such as by counting activities. The sensor may optionally serve as a user control interface for many different devices by generating control signal(s) based on identification of one or more different motion gestures.

Abstract: The conductive wire is bonded to the front electrode of the semiconductor device at the bonding section. The first resin member covers at least one end portion of two end portions of the bonding section, the first surface of the front electrode, and the second surface of the conductive wire. The second resin member covers the bent portion of the first resin member. The first resin member has a higher break elongation and a higher break strength than the second resin member. The second tensile elastic modulus of the second resin member is greater than the first tensile elastic modulus of the first resin member. Thereby, the reliability of the power semiconductor module is improved.

Abstract: A display apparatus comprises a display panel including a pixel area in which a plurality of pixels is disposed and a peripheral area outside the pixel area; a transmissive light source disposed in a first area of the pixel area; and a timing controller which controls the transmissive light source not to emit light when pixels disposed corresponding to the first area of the pixel area among the plurality of pixels are present in at least one of an image data input period and a pixel light emission period.

Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.

Abstract: A novel and useful system and method for eliminating settling time delays in a radar system. In one embodiment, a plurality of oscillators is provided with a single transmitter. In an alternative embodiment, a plurality of transmitters is provided, each with its own oscillator. In either case, more than a single oscillator is used, whereby startup or turn on transients associated with one oscillator are allowed to settle out while another oscillator is being used. The two or more oscillators switch off and/or alternate or rotate such that oscillator settling time between chirp transmissions from the radar is substantially or completely eliminated. In a radar system having two transmitters, when the chirp propagation time window for the first transmitter is complete, the first transmitter is disconnected from the receive channel and the second transmitter is connected to the antenna and receive channel without having to wait for the second transmitter to settle since it was allowed to settle beforehand.

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.