Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.

Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory has first regions in which data writes and data reads can be executed in parallel. Each of the first regions has second regions which are each a data write/read unit. The controller acquires first values indicating a data write load for each of the first regions, detects a first region having a first value greater than or equal to a first threshold, acquires second values indicating a data write load for each of the plurality of second regions in the detected first region, detects a second region having a second value greater than or equal to a second threshold but less than or equal to a third threshold that is higher than the second threshold, and then move data from the detected second region to a second region in another first region.

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.

Abstract: Systems and methods are provided for managing data partitions in a distributed storage system and, in particular, the routing data used by the distributed storage system to route requests to the proper caching layers, persistent storage nodes, etc. Data items may be managed in a multi-tier configuration in which they are grouped into different partitions based on their key prefixes, and partitions are grouped into different cells based on key ranges. When partitions are moved from cell-to-cell, or when cells are split, the routing data is changed accordingly. In order to ensure that the correct routing data is used throughout the distributed storage system, a change to routing data may be accompanied by a special barrier record being written to the transaction log of affected partitions.

Abstract: Recovering from system faults for replicated datasets, including: receiving, by the cloud-based storage system, a request to modify a dataset that is stored by the cloud-based storage system, wherein the dataset is synchronously replicated among a plurality of storage systems that includes the cloud-based storage system, wherein a request to modify the dataset is acknowledged as being complete when each of the plurality of storage systems has modified its copy of the dataset; generating recovery information indicating whether the request to modify the dataset has been applied on all storage systems in the plurality of storage systems synchronously replicating the dataset; and after a system fault, applying a recovery action in dependence upon the recovery information indicating whether the request to modify the dataset has been applied on all storage systems in the plurality of storage systems synchronously replicating the dataset.

Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.

Abstract: Managing storage systems that are synchronously replicating a dataset, including: detecting a change in membership to the set of storage systems synchronously replicating the dataset; and applying one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset, wherein the one or more membership protocols include a quorum protocol, an external management protocol, or a racing protocol, and wherein one or more I/O operations directed to the dataset are applied to a new set of storage systems.

Abstract: A storage device includes a first memory device, a second memory device and a storage controller. The first memory device buffers a plurality of unit time interval data. The plurality of unit time interval data are received in each of a plurality of monitoring time intervals. The second memory device stores at least one of the plurality of unit time interval data. The storage controller controls an amount of data flushed from the first memory device to the second memory device based on one of first and second flush commands. The storage controller compares a shock measurement value representing a magnitude of an external shock with a shock reference value. When the shock measurement value is less than or equal to the shock reference value, the storage controller provides the first flush command to the first memory device to flush first unit time interval data.

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

Abstract: A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Abstract: In some examples, a computer system computes a rate of operations that involves a first system, and classifies, using a classifier, a request for an operation. The computer system determines a relationship between the computed rate of operations and a dynamic threshold rate determined during a training phase, and based on the determined relationship and a classification of the request by the classifier, selectively activates or disables an operational feature of the first system.

Abstract: A memory system may include a storage medium including a buffer region and a main region; and a controller configured to, when performing a flush operation, move normal data from the buffer region to the main region and maintain pinned data in the buffer region, wherein the pinned data is data which is determined by a host device to be maintained in the buffer region irrespective of the flush operation.

Abstract: According to one embodiment, a memory system writes first write data into each non-defective physical block belonging to a first write destination block group. The memory system notifies a host of a first identifier of the first write data, an address specifying the first write destination block group, a first offset indicating a top write destination physical storage location in the first write destination block group in which the first write data is written, length of the first write data, and first bitmap information including a plurality of bits, each of the bits corresponding to each of physical blocks belonging to the first write destination block group and indicating whether or not the corresponding physical block is a defective block.

Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Abstract: Methods and systems for increasing reliability of a data storage device are disclosed. During fabrication runs of a non-volatile memory (NVM) die, such as a NAND, there may be a number of memory cells designated as erase cells. When one or more erase cells are physically adjacent to programmed memory cell, electrical effects of the erase cell may cause a bit to flip in the adjacent good memory cell. To mitigate this effect, an LDPC engine is used to generate additional parity bits for the erased bit/cells. When a host requests data from the NVM, the parity bits may be used to correct additional errors because of the erased state to programmed state bit flips.

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.