Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to determine a set of requirements for a persistent storage media based on input from an agent, dedicate one or more banks of the persistent storage media to the agent based on the set of requirements, and configure at least one of the dedicated one or more banks of the persistent storage media at a program mode width which is narrower than a native maximum program mode width for the persistent storage media. Other embodiments are disclosed and claimed.

Abstract: The present teaching relates to a method, system and programming for operating a data storage. The data storage comprises of different portions including: a first portion having a plurality of metadata objects stored therein, each of the metadata objects being associated with a filter and corresponding to a range of keys, wherein at least one of the metadata objects is associated with a data structure, and a second portion having a plurality of files stored therein, each of the plurality of files being associated with one of the plurality of metadata objects; The data storage synchronizes a scan request with respect to one or more write requests based on a parameter associated with the scan request and each of the one or more write requests.

Abstract: Methods, computer program products, computer systems, and the like for efficient metadata management are disclosed, which can include receiving a subunit of storage, storing a first metadata portion of the subunit of storage in a first unit of storage, and storing a second metadata portion of the subunit of storage in a second unit of storage.

Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

Abstract: Systems and methods are provided for storing data blocks in distributed storage. One example computer-implemented method includes, in response to receipt of a data block comprising data, generating a value N for the data block, wherein the value N includes a variable integer greater than one and dividing the data block into N segments, wherein each segment includes a portion of the data. The method also includes generating a value M for the data block, wherein the value M includes a variable integer greater than or equal to one, and adding M segments of chaff to the N segments. The method then includes encrypting the N segments and the M segments of chaff and distributing the M segments and the N segments in distributed storage, wherein the N segments and the M segments of chaff are stored in multiple different storage devices included in the distributed storage.

Abstract: A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.

Abstract: A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; translate a combination of the first integer value and the second integer value to a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state and a third set of logical bits corresponding to the second Vt state.

Abstract: A data storage apparatus may include a storage and a controller. The storage includes a plurality of planes each composed of a plurality of memory blocks, and is divided into a first region and a second region. An original of system data and a copy of the system data are stored in the first region. The controller is configured to perform a relief operation of moving the copy of the system data stored in a source memory block of the first region to a victim plane and switching the source memory block to a region replaceable with the second region.

Abstract: Techniques are provided for forwarding operations to bypass persistent memory. A modify operation, targeting an object, may be received at a persistent memory tier of a node. If a forwarding policy indicates that forwarding is not enabled for the modify operation and the target object, then the modify operation is executed through a persistent memory file system. If the forwarding policy indicates that forwarding is enabled for the modify operation and the target object, then the modify operation is forwarded to a file system tier as a forwarded operation for execution through a storage file system.

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a plurality of data blocks, a plurality of replacement blocks to replace bad blocks, and a system block configured to store default system information. The memory controller may store, based on a result of comparing a lifetime of the memory device with a reference value, update system information corresponding to an update of the default system information, in a selected replacement block among the plurality of replacement blocks. The memory controller may control the memory device to set the selected replacement block as a target system block. The default system information may include one or more parameters corresponding to at least one operation among a read operation, a program operation, and an erase operation of the memory device.

Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of the memory cells. The encoded data is decoded and error corrected. Therefore, the original data that was programmed into the memory cells is recovered. The group of memory cells are sensed at candidate soft bit reference levels, and possibly other reference levels. For each candidate soft bit reference level, mutual information between the original programmed data and the data for that candidate soft bit reference level is determined. The mutual information serves as a good measure for how well the candidate soft bit reference level will aid in decoding the data. In an aspect, a soft bit reference level having the highest mutual information out of several candidates is selected as the calibrated soft bit reference level.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

Abstract: A method for reprogramming data of a software function executed by an execution core and a security core, the data being present in two physically separate non-volatile memories, each managed by one of the execution or security cores, including the following steps: upon receiving a reprogramming request, a second value is stored in a first Boolean, determining whether the first Boolean is equal to the second value and if a second Boolean is equal to a first value, and if affirmative; an execution core is made to emit at a reinitialization request via a bidirectional communication channel towards a security core and a request to initialize a portion of the first non-volatile memory towards the set of functions for managing the non-volatile memory by an execution core; a second value is stored in the second Boolean; it is determined whether a predetermined reprogramming event has taken place, and if affirmative, the first value is stored in the first Boolean, while keeping the second value in the second Boolean

Abstract: The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.

Abstract: Data employed in computations is processed so that during computations more of the data can be fit into or maintained in a smaller but higher speed memory than an original source of the data. More specifically, a sensitivity value is determined for various items of the data which reflect the number of bits in the data items that are not garbage bits, and only information in the data items that are indicated by the sensitivity value to not be garbage bits are necessarily effectively retained. At least the information that is not garbage bits and the corresponding associated sensitivity are packed together. The results of computations that are performed using the data items as at least one of the operands for the computation are associated with a sensitivity that is derived from the individual sensitivities of the operands used in the computation.

Abstract: In an approach to extending the lifespan of a flash-based storage device, responsive to receiving a signal from a storage device that the storage device is low on extra blocks, one or more free logical blocks that are no longer needed are released. The storage device is notified of the one or more free logical blocks that are no longer needed. Responsive to determining that the number of valid physical blocks is greater than the number of used logical blocks, the advertised capacity of the storage device is reduced.

Abstract: Accessing additional storage space of a storage system includes reading a physical data fragment that is an incremental subset of a physical storage unit of the storage system, accessing metadata corresponding to logical blocks stored on the physical data fragment to determine a sidebar storage portion of the physical data fragment that is unused by the logical blocks, and accessing data of the sidebar storage portion. Accessing data of the sidebar storage portion may include providing data from the sidebar storage portion to a calling process. Accessing data of the sidebar storage portion may include modifying a portion of data from the physical data fragment and writing the physical data fragment back to the physical storage device. The physical data fragment may be locked prior to reading the physical data fragment and the physical data fragment may be unlocked after writing the physical data fragment.

Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Abstract: A data transfer device including an enclosure with a plurality of input/output connection ports, a processor, a memory including a data store, and a data transfer component. The data transfer component directs the processor to transfer data from an external data source via at least one of the plurality of input/output connection ports, encrypt the transferred data, store the encrypted data on the data store, responsive to a successful transfer of the encrypted data to the data store, delete the data from the external data source, establish a connection to an external data storage service, responsive to a successful connection to the external data storage service, transfer the encrypted stored data to the external data storage service, responsive to a successful transfer of the encrypted stored data to the external data storage service, deleting the encrypted stored data from the data store.