Abstract: A method and apparatus for measuring a dimension of a workpiece mounted on a numerically controlled machine tool having a probe for sensing the surface of the workpiece, an automatic means for moving the probe relative to a datum, the automatic means including a first measuring means for producing a signal defining units of distance corresponding to the relative movement of the probe with respect to the datum, and a second measuring means coupled to the first measuring means for accumulating a count corresponding to the relative movement of the probe in respect to the datum. The actual position of the workpiece surface is determined relative to a nominal position thereof, the nominal position being at a known distance from the datum. According to the method the probe is moved to a first position which is one of the actual and nominal positions of the workpiece surface.

Abstract: A spelling error detector apparatus employs a memory which stores alphabetical words as those existing in the English language in three major memory sections which constitutes a most frequently used word list (MFU), a master word list (MWL) and a personal word list (PWL). Each word is uniquely coded and stored as a 24 bit binary number. The system then retrieves words which are stored or entered into a processor memory and which words are indicative of a document to be printed. Each word emanating from the processor memory is converted into the same code as the stored words and then a search is made to determine whether the processor word compares with a word as stored. If a favorable comparison is had, it is assumed that the spelling of the processor word is correct. If an unfavorable comparison is had, it is assumed that the spelling is incorrect and the misspelled word is stored in a separate memory which can be accessed by the operator in order to make the necessary corrections.

Abstract: An arbitration controller providing for equal priority sharing of a resource by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: This circuit provides a minimally sized bidirectional asynchronous automatic interface between a high speed data processing system and one of a plurality of data terminal devices.

Abstract: A digital data display in which each display unit includes a random access, read/write character definition buffer store and a screen buffer. The character definitions and screen buffer for each picture to be displayed are constructed in a remote host central processing unit. In order to minimize the time that a user has a blank screen while new character definition and screen buffer data is sent from the c.p.u. to the display unit, this information is sent in groups relating to rows of character cells on the screen and a coherent picture is displayed growing from the top downwards, giving a roller blind effect. Data relating to the first significant row is sent initially followed by groups of character definitions and screen buffer data, the size of the groups dependent upon the characteristics of the transmission buffer.

Abstract: An arbitration controller providing for equal priority sharing of duplicate copy resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPUs for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2.sup.n addresses such that there is paged and unpaged ROM and paged and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory.

Abstract: An arbitration controller providing for equal priority sharing of a resource by a plurality of central processing units. Conflicts resulting from simultaneous requests from several CPU's for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: A system to improve traffic flow on all types of interconnected roadways, which reduces fuel consumption, emissions and trip times, is based on adaptive control of traffic signal timing. The parameters used to exercise this control are generated by sensing presence, duration, time, and velocity of vehicles passing a narrow road segment upstream from the signallized intersection and with intersections in proximity to each other, also downstream from that intersection. The information generated by each sensor is processed into three running aggregate quantities; aggregate momentum data, aggregate experienced congestion data and aggregate stopped vehicles data. A fourth quantity, triggered by tentative platoon identification, is based on velocity and density of a small sample of vehicles and speeds response time to an approaching platoon by pre-empting signal timing briefly.

Abstract: There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave processor can access only its respective memory, the master processor can access either its own memory or any one of the slave memories. Maximum throughput (efficiency) is achieved by suspending operation of a single slave processor for only a single memory cycle, i.e., the time required for the master processor to access the respective slave memory. Each processor/memory is on a single card, with all of the cards being connected to a common bus. The cards are virtually identical, and master/slave distinctions are determined by a single slot bit on each card. A unique addressing scheme is implemented for access from the master to a selected slave.

Abstract: Latency of a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities is reduced without modification of the channel and CPU hardwares. The storage device is divided into a plurality of randomly accessible pages each having parallel cyclic tracks. Each page is subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Parallel bits on different tracks form bytes. Data are transferred byte by byte between a selected page of the device and a specified one-page data area in the main storage. A channel program is constructed using three commands (CCWs); a Seek Page command followed by two different Read or Write commands. At the end of the Seek Page operation, a control unit determines which of Sector 0 or 1 is more immediately accessible.

Abstract: A computer monitoring system connects into the channel (24), serving as a link between a CPU (10) and peripheral devices (12), (14), (16). Channel signals are extracted in a channel interface module (18), altered to be compatible with the logic in a data collection module (20) and sent to a data collection module (20) along with event codes generated within the channel interface module (18) to indicate certain sequences and/or combinations of signals occurring on the channel (24). The data collection module (20) is programmable to select those peripheral devices it wants to monitor and the type of information to be collected. The data collection module (20) also includes circuitry for counting the number of successive search commands performed for a device without collecting the information contained therein for each command as well as circuitry for measuring the percentage of activity of each device and the channel as a whole.

Abstract: System for controlling the duration of the time interval between the blocks of data transmitted by a computer 1. A channel 7 transfers the first block to be transmitted to a control unit 2 which sends same over a line 4 through a modem 3. When the block has been transmitted, the unit 2 signals the channel accordingly and receives therefrom a command specifying the duration of the time interval between the blocks. The unit 2 activates interval timing means and signals the channel 7 when the time interval has elapsed. The channel can then send the second block to the unit 2.

Abstract: An arbitration controller providing for equal priority sharing of duplicate copy resources by a duplex plurality of central processing units. Conflicts resulting from simultaneous requests from several CPU's for access to the common resource are resolved at a high rate of speed. In addition, an approximately statistically equal probability is maintained for access of the common resource by all the central processing units.

Abstract: A power measuring device is disclosed featuring the capability of converting resistively coupled load current and voltage signals to a digital pulse train whose frequency is proportional to the instantaneous power drawn. The digital pulse train can be optically coupled to a microcomputer-based display or process controller for conversion of the pulse train frequency to a power consumption indicating signal.

Abstract: Adaptive bit allocation optimizes the encoded transmission of speech signal parameters. Allocation is controlled by a voiced/unvoiced decision signal derived from occurrence rate distributions of Partial Correlation Coefficient K1.

Abstract: An indicator system satisfies multiple flight-mission requirements by providing an aircraft pilot with a visual display consisting of a movable map and navigational data. The map is stored in video form in a high-capacity compact mass memory consisting of a video disk. The system further comprises a symbol and character generator as well as an intermediate memory which has a capacity larger than required for the map-zone image to be displayed together with navigation symbols on a television monitor. The unit is controlled by a microprocessor on the basis of data relating to latitude, longitude and heading of the aircraft in order to refresh the intermediate memory and to obtain an image displayed with a "top-north" or "top-heading" orientation.

Abstract: An instrument is disclosed which performs measurements and calculates the average and the variance of the measurements. The particular instrument illustrating the invention is a spectrophotometer which measures sets of dark, reference and sample spectra for use in calculating an average absorbance spectrum and its variance. The measurements are performed in an order which enables the cancellation of measurement variation due to variation in instrument response. The order of measurements is determined by measurement subroutines which can be aggregated to produce a series of measurements performed over a user selected period of integration time.

Abstract: Integrated circuit speech synthesis system utilizing complementary metal-insulator-semiconductor technology to achieve low voltage operation, wherein a pluse width modulated digital-to-analog converter is employed to provide for accurate conversion of digital signals into analog signals even though the low voltage operation prohibits the large voltage swings normally required for digital-to-analog converter circuitry. The speech synthesis system includes a linear predictive filter as a speech synthesizer which utilizes coded reflection coefficients to produce digital signals representative of human speech. A microprocessor controls the access of digitized speech data which is stored in a memory. The speech synthesizer and microprocessor along with the pulse width modulated digital-to-analog converter are implemented in complementary metal-insulator-semiconductor technology.

Abstract: A Fault-Tolerant Multi-Computer System for control applications is disclosed. The system has a plurality of Computers (10a-10n), each having an assigned set of tasks which it is capable of executing. No one Computer in the system acts as a master and no one Computer executes all of the tasks. Communication between the Computers is by individual communication links (16, 18, 20) over which each Computer sends information directly to all other Computers in the system. Each Computer comprises an Applications Computer (100) and an Operations Controller (200). The Operations Controller receives messages over the communication links and selects, from the assigned tasks, the tasks to be performed by the associated Applications Computer. Each Operations Controller includes a fault handler which checks the messages received from the other Computers. The fault handlers send and receive error messages, over the communication links, to assist in the identification of a faulty Computer.