Patents Examined by Mark P. Watson
  • Patent number: 4441163
    Abstract: A data communications system to provide for the dynamic modification of a queue of documents arranged sequentially for transmission. An operator interacts with the send queue by making the send queue selection from a menu of communication request tasks on a display. Selection of the addition to the send queue option invokes a routine to add a send job. Operator selection of the display send queue option invokes a routine to display the send queue in the display for review of the current send queue and its status. A delete send job option invokes a routine to allow the operator to delete any job from the send queue except the one currently being sent. The select next send job option invokes a routine to allow the operator to start or restart the sending process from any point within the send queue.
    Type: Grant
    Filed: June 16, 1981
    Date of Patent: April 3, 1984
    Assignee: International Business Machines Corporation
    Inventors: Gary E. Leikam, Robert L. Wierwille, Rebecca S. Wood
  • Patent number: 4439837
    Abstract: An intelligent terminal comprising a first memory system (bubble memory) for storing data including a plurality of function programs; a second memory system (static RAM) and a processor operatively coupled to the static RAM to execute instructions therefrom at high speeds. A keyboard is used for selecting a function program to be executed and a direct memory access controller is used for transferring data, including a function program which is selected by the keyboard, from the bubble memory to the static RAM to enable the processor to execute the selected function program. A comparator is used for determining the end of a selected function program, and a static scratch pad RAM is used to store changes made in data to be returned to the bubble memory.
    Type: Grant
    Filed: June 16, 1981
    Date of Patent: March 27, 1984
    Assignee: NCR Corporation
    Inventors: Peter P. Aiena, Eduard Schulz
  • Patent number: 4439829
    Abstract: A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: March 27, 1984
    Assignee: Wang Laboratories, Inc.
    Inventor: Horace H. Tsiang
  • Patent number: 4437170
    Abstract: A method and circuit arrangement for the acceptance and temporary storage of data signals in a data switching system includes a data communication control to which the data signals are supplied, a connection memory which makes information available to the data communication control, and a memory arrangement for serving as the data storage. The connection memory stores the address of a memory area within the memory arrangement which is available for the acceptance and temporary storage of data signals in the connection memory for each line section. In response to the first activation of such a memory area, the addresses of additional memory areas are made available to the data communication control.
    Type: Grant
    Filed: July 20, 1981
    Date of Patent: March 13, 1984
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerhard Moschitz, Richard Schoonhoven
  • Patent number: 4437169
    Abstract: A stage lighting control system having a main processor unit and a portable desk controller, wherein a local microprocessor is provided in the portable desk controller to scan the dimmer control contacts in the desk and to transmit changed state control data to the main processor as an asynchronous serially coded signal on a low capacity link which enables the controller to be conveniently located remote from the main processor. Changed display data is developed by a visual display unit (V.D.U.) interface in the main processor for transmission on the low capacity link as standard composite video to a V.D.U. at the desk. Output to the dimmers circuitry is through an expansible plurality of output channel processors controlling groups of dimmers for efficient data formatting. Lighting level information is recorded in accordance with a channel code, patching means being provided to enable differing arrangements of dimmers circuitry to be controlled in accordance with the recorded lighting level information.
    Type: Grant
    Filed: May 1, 1981
    Date of Patent: March 13, 1984
    Assignee: The Rank Organisation Limited
    Inventors: David R. Bertenshaw, Edwin P. Lockwood, Anthony R. Brown
  • Patent number: 4437155
    Abstract: When a processor issues a read or write command to read one or more words from a disk, a cache store is checked to see if a copy of the segment(s) containing the word(s) are present therein. If a copy of the segment is not present in the cache store then it is moved from disk to the cache store and sent to the processor. A segment descriptor table is maintained and the entries in the table are linked by forward and backward age links. When a segment is brought into the cache store from a disk because it contains the word or words specified by a command, its segment descriptor is linked in the age chain as the most recently used. Provision is made for reading into the cache store one or more segments in addition to the segment(s) containing the word(s) specified by a command, on speculation that the additional segment(s) contain words most likely to be accessed soon by the processor.
    Type: Grant
    Filed: November 14, 1980
    Date of Patent: March 13, 1984
    Assignee: Sperry Corporation
    Inventors: Daniel D. Sawyer, Marvin J. Thompson
  • Patent number: 4432054
    Abstract: A duplex transmission control system having active and inactive systems for totally controlling a looped transmission line on which computers and terminal devices are connected through respective stations. Each transmission control unit is operable to transmit and receive specific data related to the priority level specified for each unit. Each transmission control unit suspends the transmission of the clock for a certain period in response to the detection of the clock suspension, then transmits the specific priority data. When a transmission control unit detects its own transmitted signal, it is designated as the active system when another transmission control unit receives the signal defining the active system, it is designated as the inactive system.
    Type: Grant
    Filed: August 28, 1981
    Date of Patent: February 14, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Okada, Hitoshi Fushimi, Seiichi Yasumoto, Takuji Hamada
  • Patent number: 4430707
    Abstract: A digital data processor operates at a microinstruction level in a multiprocessing and multiprogramming environment. The processor includes multi-phase subroutine control apparatus which provides for multiple levels of subroutine entry for a plurality of concurrently executing tasks, while also permitting the tasks to share the same subroutines. Tasks and subroutine control operations are staged to employ common hardware in a manner which provides the effect of a plurality of separate processors operating concurrently on different tasks in a multi-phased manner.
    Type: Grant
    Filed: March 5, 1981
    Date of Patent: February 7, 1984
    Assignee: Burroughs Corporation
    Inventor: Dongsung R. Kim
  • Patent number: 4429362
    Abstract: A buffer can exchange data between a computer having a plurality of lines and a device. One of these lines, a halt line, can transmit a halt signal when the computer has halted. The buffer includes a plurality of transmitters and a plurality of controlled receivers. A halt transmitter is included among the plurality of transmitters. The transmitters are separately connected to predetermined respective ones of the plurality of lines for transmitting their signals to the device. The halt transmitter is connected to the halt line for transmitting the halt signal to the device. The receivers are connected between the device and given respective ones of the plurality of lines for coupling to them signals from the device. Each one of a predetermined set from the plurality of receivers has a receive terminal commonly connected to the halt line for enabling operation of this predetermined set in response to the halt signal.
    Type: Grant
    Filed: June 18, 1981
    Date of Patent: January 31, 1984
    Assignee: The Bendix Corporation
    Inventor: John J. Costantini
  • Patent number: 4429363
    Abstract: In a storage hierarchy, promotion of data from a backing store to a caching buffer store is restricted based upon status of the cache and activity of a last storage reference. Observed writing activity selectively inhibits data promotion. Data promotion occurs after completion of a series of storage access requests. A peripheral data storage system is described.
    Type: Grant
    Filed: October 15, 1981
    Date of Patent: January 31, 1984
    Assignee: International Business Machines Corporation
    Inventors: Alan H. Duke, Michael H. Hartung, Frederick J. Marschner
  • Patent number: 4428063
    Abstract: A device for the time compression of a continuous sequence of data, so as to effect compression in a ratio k=p/n (p and n being positive integers, p not being a factor of n and n not being a factor of p), the ratio p/n representing the ratio of time required for transmission of data after compression to the time required for transmission of the same data before compression. Two memories and a control circuit generate clock signals to fill one of the memories with a package of N bits while emptying the other one. The control circuit receives a clock signal whose frequency is Fu, and divides its frequency by n and by p to generate a clock signal whose frequency is Fu/n and p clock signals whose frequencies are Fu/p and whose phases are shifted of 2.pi./p from one to another. A multiplexer selects one of these p clock signals, at the time when storing and writing of each package of data begins, in order to generate a read clock signal and a write clock signal which are in phase.
    Type: Grant
    Filed: September 29, 1981
    Date of Patent: January 24, 1984
    Assignee: Thomson-CSF
    Inventor: Pierre Fourcade
  • Patent number: 4426682
    Abstract: A fast cache flush mechanism includes, associated with the cache, an auxiliary portion (termed a flush count memory) that references a flush counter during the addressing of the cache. This flush counter preferably has a count capacity of the same size as the number of memory locations in the cache. Whenever the cache is updated, the current value of the flush counter is written into the location in the flush count memory associated with the memory location in the cache pointed to by an accessing address, and the valid bit is set.Whenever it is desired to flush the cache, the contents of the flush counter are changed (e.g. incremented) to a new value which is then written as the new cache index into the location of the flush count memory associated with that flush count, and the associated valid bit is cleared or reset.
    Type: Grant
    Filed: May 22, 1981
    Date of Patent: January 17, 1984
    Assignee: Harris Corporation
    Inventors: Josephus Riffe, Rajiv Sinha
  • Patent number: 4425629
    Abstract: A text processing system includes a first external storage area for text documents, an internal text storage buffer where, inter alia, edit operations are performed, and a third storage area in which text is formatted for display. The area for formatting text for display is related to the internal text storage buffer by a table containing pointers to the text storage area, one for each line to be displayed. The pointers are expressed relative to a single known address, that of the start of the line in the text storage buffer containing the point at which the edit operation is to occur.
    Type: Grant
    Filed: June 16, 1981
    Date of Patent: January 10, 1984
    Assignee: International Business Machines Corporation
    Inventors: William C. Cason, Ward A. Kuecker
  • Patent number: 4424561
    Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.
    Type: Grant
    Filed: December 31, 1980
    Date of Patent: January 3, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: Philip E. Stanley, Richard P. Brown, Arthur Peters
  • Patent number: 4424565
    Abstract: The subject channel interface circuit functions in a multiprocessor environment to provide a high speed interface between a processor and the communication channel which interconnects all the processors. The communication channel carries data messages, which messages contain a header field specifying source, destination and control information. The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is received and thereby determine whether this data message is to be stored in the processor memory. If the data message is to be stored, the channel interface circuit immediately converts the header field into a hardware address, which is used to activate a specific location in processor memory. The data message is then inputted (via DMA) to this memory location and the appropriate buffer pointers are reset.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: January 3, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Allen L. Larson
  • Patent number: 4420818
    Abstract: A cassette tape recorder interface for high speed loading into a computer of data stored on cassette tapes. The interface receives signals from a cassette tape recorder modified to have the play head engaged while in the fast forward wind mode. The interface includes a comparator, a separator for separating clock and data pulses, a serial-to-parallel converter, control logic, and interface program memory.
    Type: Grant
    Filed: March 12, 1981
    Date of Patent: December 13, 1983
    Assignee: Recortec, Inc.
    Inventors: Lester H. Lee, George Wussow
  • Patent number: 4420807
    Abstract: Data associated with a defective area of a backing store and stored in an alternate area, such as defective and alternate tracks in a direct access storage device, is selectively stored in a high speed buffer front store based upon usage of such data. A first replacement control governs buffer operation for data from good areas of the backing store, and a second independent replacement control governs buffer operation for data from alternate storage areas. Limitations are imposed on the amount of data subject to the second replacement control.
    Type: Grant
    Filed: August 31, 1981
    Date of Patent: December 13, 1983
    Assignee: International Business Machines Corporation
    Inventors: Arthur H. Nolta, David G. Reed
  • Patent number: 4419728
    Abstract: The subject channel interface circuit functions to provide a high speed interface between a processor and a data link, which link carries data messages having virtual addresses. The message handler is programmable and serves to translate the header portion of the data message from a virtual address into a hardware memory address, which is used to activate a specific location in the processor memory. The data portion of the data message is then directly inputted to this memory location (i.e., DMA) and the appropriate file pointers are reset. When a complete file is received and stored in memory, the message handler generates a processor interrupt.Thus, the subject message handler performs all the data receiving tasks, including file storage and linking, without requiring the involvement of the associated processor.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: December 6, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Allen L. Larson
  • Patent number: 4419726
    Abstract: An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic "exit" microcommand to be interpreted either as a "return" or a "decode" depending upon the state of the subroutine stack.
    Type: Grant
    Filed: January 16, 1981
    Date of Patent: December 6, 1983
    Assignee: Sperry Corporation
    Inventor: Albert J. Weidner
  • Patent number: 4412300
    Abstract: A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit with a section capable of being defined by plug-in read-only memory modules and stored programs added by the user, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the calculator, and a solid state output display unit capable of displaying three lines of numeric information.
    Type: Grant
    Filed: February 6, 1981
    Date of Patent: October 25, 1983
    Assignee: Hewlett-Packard Company
    Inventors: Robert E. Watson, Jack M. Walden, Charles W. Near