Patents Examined by Mark Prenty
  • Patent number: 10170413
    Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu Ohtou, Yusuke Oniki, Hidehiro Fujiwara
  • Patent number: 10170609
    Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
  • Patent number: 10170608
    Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer
  • Patent number: 10164068
    Abstract: A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10164206
    Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Shunpei Yamazaki, Takahiro Ishisone
  • Patent number: 10164114
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 10158069
    Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
  • Patent number: 10153233
    Abstract: An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: December 11, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chi-Hao Huang, Chin-Cheng Yang
  • Patent number: 10153232
    Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
  • Patent number: 10141370
    Abstract: The invention relates to an optoelectronic device (45) including: light-emitting diodes (LED) including semiconductor elements (24); current-limiting components (50), wherein each component is connected in series to one of the semiconductor elements and has a resistance that increases with the strength of the current.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: November 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alexei Tchelnokov, Ivan-Christophe Robin, Bruno Mourey
  • Patent number: 10134870
    Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 10134731
    Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Tom Lii
  • Patent number: 10134984
    Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 20, 2018
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Joanna Bettinger, Xianliang Liu, Zeying Ren, Xu Zhao, Fnu Atiquzzaman
  • Patent number: 10128330
    Abstract: A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 13, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ralph N. Wall, Meng-Chia Lee
  • Patent number: 10128241
    Abstract: An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-soo Kim, Koung-min Ryu
  • Patent number: 10121805
    Abstract: A semiconductor structure is disclosed. The semiconductor substrate includes: a front surface and a back surface; and a heterogeneous radiation-sensing region in the semiconductor substrate, the heterogeneous radiation-sensing region including a top surface, a bottom surface and sidewalls, the top surface being adjacent to the front surface of the semiconductor substrate, the sidewalls being perpendicular to the front surface of the semiconductor substrate, and the bottom surface being parallel to the front surface of the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: November 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Chyi Liu, Yu-Hsing Chang, Yung-Chang Chang, Shih-Chang Liu
  • Patent number: 10121816
    Abstract: An imaging device includes a plurality of pixels. Each of the pixels includes a photoelectric conversion unit provided in a first semiconductor region of a first conductivity type, a transfer transistor including a second semiconductor region of a second conductivity type to which charge generated in the photoelectric conversion unit is transferred, a third semiconductor region of the first conductivity type provided in a portion deeper than the second semiconductor region and having a higher impurity concentration than the first semiconductor region, and a counter doped region provided around the second semiconductor region. A part of the third semiconductor region and a part the counter doped region are overlapped with a gate electrode of the transfer transistor in a plan view. An overlap of the counter doped region with respect to the gate electrode is larger than an overlap of the third semiconductor region with respect to the gate electrode.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: November 6, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Junji Iwata
  • Patent number: 10121878
    Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Jagar Singh, Hui Zang
  • Patent number: 10112825
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Patent number: 10109502
    Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott