Patents Examined by Mark Prenty
  • Patent number: 9853177
    Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 26, 2017
    Assignee: First Solar, Inc.
    Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
  • Patent number: 9852995
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface with a semiconductor element and a second surface opposing the first surface. A first metal layer has a third surface supporting the first semiconductor chip and a fourth surface opposing the third surface. The third surface is larger than the second surface. A resin layer has a fifth surface facing the first semiconductor chip and a sixth surface facing the first metal layer. A pad is on the first surface of the first semiconductor chip. A first via contact is within the resin layer on the third surface of the first metal layer. A second via contact is within the resin layer on the pad. The first and second via contacts are connected to first and the second interconnects, respectively.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: December 26, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Mori, Chiaki Takubo
  • Patent number: 9837605
    Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pei Hsieh, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9837320
    Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: John C. Pritiskutch, Richard Hildenbrandt
  • Patent number: 9831317
    Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Tek Po Rinus Lee
  • Patent number: 9831299
    Abstract: An OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring 5 which conducts with an earth line of a flexible printed substrate 15 is provided on a substrate 1. A display area 2 comprised from a plurality of OLED elements is provided at the center of the substrate 1 and four low resistance metal films 3 are provided along each of four edges of the display area 2 on a surface of insulation films 8, 10 at the periphery of the display area 2. Among these, one low resistance metal film 3 conducts with the metal wiring 5 via a contact 3a.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: November 28, 2017
    Assignee: Japan Display Inc.
    Inventors: Kouhei Takahashi, Hirotsugu Sakamoto, Takeshi Ookawara, Toshihiro Sato
  • Patent number: 9825019
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, and first and second electrodes on the layer. A first region of the first type is between the layer and the first electrode and contacting the first electrode. A second region of a second conductivity type is between the layer and the second electrode. A third region of the second type is connected to the second electrode, between the first and second regions, and between the layer and the second electrode. A fourth region of the first type is between the second region and the second electrode and contacting the second electrode. A fifth region of the second type is between the layer and the second region and has an impurity concentration greater than the second region and the third region. A sixth region of the first type is between the second region and the third region.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Sai
  • Patent number: 9818915
    Abstract: A manufacturing method of a LED display is provided. A temporary substrate is provided, wherein the temporary substrate has a first adhesive layer and a plurality of first, second and third LED chips mounted on the first adhesive layer. A first transparent substrate is provided, the transparent substrate has a plurality of pixels disposed thereon, and each of the pixels comprises a first sub-pixel, a second sub-pixel and a third sub-pixel respectively surrounded by a light-insulating structure. Then, the temporary substrate and the first transparent substrate are bonded together, such that each of the first, second and third LED chips is correspondingly mounted in each of the first sub-pixels, the second sub-pixels and the third sub-pixels. After that, the temporary substrate is removed. A LED display manufactured by said method is also provided.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 14, 2017
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chia-En Lee, Chia-Hung Hou
  • Patent number: 9818705
    Abstract: A semiconductor device includes at least one semiconductor element having a first terminal side and a second terminal side connected by an outer periphery portion, a first terminal on the first terminal side, and a second terminal on the second terminal side. The device includes a frame surrounding the outer periphery portion of the semiconductor element. A first electrode is on the first terminal side and is electrically connected to the first terminal. The first electrode includes a first body portion and a first projection protruding outwardly therefrom around the circumference of the first body portion. A second electrode is on the second terminal side and is electrically connected to the second terminal, and a metal plate is over the first electrode. The first projection of the first electrode is spaced from and extends along a peripheral portion of the metal plate.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: November 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshimitsu Kuwahara
  • Patent number: 9806113
    Abstract: Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sun Oh, Kyung-Ho Lee, Jung-Chak Ahn, Hee-Geun Jeong
  • Patent number: 9806178
    Abstract: A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material, recessing the fin to form a trench over a lower portion of the fin, growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process, forming a first carbon doped layer over the lower portion through a second epitaxial process, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin through a third epitaxial process, forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9793184
    Abstract: A semiconductor arrangement is presented.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Riegler, Angelika Koprowski, Mathias Plappert, Frank Wolter
  • Patent number: 9786783
    Abstract: Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Joodong Park, Jeng-Ya D. Yeh, Chia-Hong Jan, Curtis Tsai
  • Patent number: 9780216
    Abstract: An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tsu-Hsiu Perng, Tung Ying Lee, Ming-Huan Tsai, Clement Hsingjen Wann
  • Patent number: 9780131
    Abstract: An image sensor may include a substrate having a photoelectric conversion element and a grid pattern formed over the substrate and having a flat upper surface, a first side surface, and a second side surface, wherein the first side surface and the second side are located opposite to each other. A first internal angle is formed between the flat upper surface and the first side surface, a second internal angle is formed between the flat upper surface and the second side surface, and the first internal angle may be smaller than the second internal angle.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 3, 2017
    Assignee: SK Hynix Inc.
    Inventors: Donghyun Woo, Yun-Hui Yang
  • Patent number: 9771258
    Abstract: A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 26, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Buu Q. Diep, Adam M. Kennedy, Thomas Allan Kocian, Mark Lamb
  • Patent number: 9768208
    Abstract: An organic light emitting display includes a pixel circuit to supply current to an organic light emitting device. The pixel circuit includes a switching transistor and a driving transistor. The switching transistor includes a first insulating layer between a first gate electrode and an oxide semiconductor layer. The driving transistor includes a second gate electrode on an active layer. The first insulating layer is between the active layer and the second gate electrode.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Chaun-Gi Choi
  • Patent number: 9768241
    Abstract: A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 19, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Se Lee, Won-Kyu Kwak, Se-Ho Kim
  • Patent number: 9761798
    Abstract: A storage device of an embodiment includes a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element, a second conductive layer including a first region containing a first metal element and carbon or nitrogen, a second region containing a second metal element and carbon or nitrogen, and a third region provided between the first region and the second region, the third region containing a third metal element, the standard free energy of formation of an oxide of the third metal element being smaller than the standard free energy of formation of an oxide of the first element, a ferroelectric layer provided between the first conductive layer and the second conductive layer, and a paraelectric layer provided between the first conductive layer and the ferroelectric layer.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuuichi Kamimuta, Shosuke Fujii, Masumi Saitoh
  • Patent number: 9761499
    Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek