Abstract: A device for checking the printing circuit of a thermal printer wherein pulse currents are passed through only those of the heaters which correspond to printing data stored in a shift register via a power supply resistor and driver transistors to energize the corresponding heaters so as to effect color printing for one operation on heat-sensitive paper. The device comprises a self-examination control section for effecting at least one of the three types of checking, i.e., a check on the driver transistors for malfunction, a check on the heaters for malfunction, and a check on the shift register for malfunction, the arrangement being such that the printing circuit is automatically checked without actual printing operation by making use of the waiting time in which the thermal printer is not printing.Checking the printing circuit by the present device avoids delay in printing and dispenses with manual operation for checking.

Abstract: An interlocking system comprising a plurality, e.g., three, of parallel sub-systems operating asynchronously to produce identical replicated outputs which are mutually compared to determine the correct output and disqualifying a minority output thereby ensuring high system integrity. Each sub-system includes a similar arrangement for computing the difference between all possible pairs of sub-systems. Comparison of these results with a reference table of all possible difference results and then comparison of the difference equations yields a common factor which is the sub-system producing the error. Action can then be taken to disqualify its output, e.g., by switching-off its power supply. A final output is taken, preferably from one sub-system, with a second as standby.

Abstract: An apparatus for operational analysis of computing devices which, when coupled to the address, data, and control buses of a computer, displays a representation of a selectable subgroup of the bus signals on a bit map display for each occurrence of a selectable condition. The bits of the least and most significant halves of the selected subgroup define the horizontal and vertical coordinates of a display pixel activated upon occurrence of the selectable condition. Selectable groups are address and data bus signals. An optional condition is specification of bit values of signals on the buses. Selectable control bus signal conditions are read or write and input/output or memory. The display is latched with the state of the selectable subgroup upon occurrence of the selectable conditions thereby remaining stable until the next occurence of the selectable conditions.

Abstract: In a system which is provided with a key storage having stored therein main storage keys respectively corresponding to pages into which a main storage is split, each main storage key having at least a reference bit indicating whether the corresponding page is being accessed and a change bit indicating whether information has been written in the page, and in which a parity bit is added to each of the reference bits and the change bits to form the main storage key.

Abstract: A bus fault location arrangement for locating the source of a fault condition on a bus connecting a plurality of devices energized by a power supply. When such a fault condition is detected, a bus diagnostic unit included in the arrangement transmits a signal to place a given one of the plurality of devices in a high impedance state. The bus diagnostic unit then transmits a given signal level on the bus. To determine whether the given device is the source of the fault condition, current flow between the device and the power supply is sensed and an error signal is stored when the sensed current exceeds a predetermined magnitude.

Abstract: A method and apparatus for storing data in which the data is checked for an error without requiring the data to include an error correction code. Included in the system is a logic circuit for dividing a data word by a polynomial during the time the data word is being written into the primary memory unit resulting in the generation of a remainder which is stored in an auxiliary memory unit. When reading the data word from the primary memory unit, the data word is again divided by the same polynomial and the remainder compared with the remainder stored in the auxiliary memory unit. If the remainders match, no error was introduced during the storing of the data in the main memory unit. If the remainders do not match, an error is indicated. This system allows a data word to be stored in a main or primary memory unit without requiring the word to include error correction bytes.

Abstract: A circuit and method are disclosed for testing line replaceable units (LRUs) and interconnect buses of an avionics system in which the various LRUs exchange information by means of transmitting and/or receiving digital communication words, each word having a predetermined, standardized serial bit format. A stream of communication words, each comprised of a predetermined number of bits, is serially received and converted to parallel format by a shift register that cooperates with a word counter also coupled to the stream of words, so as to output successively and in parallel format, each communication word. A general purpose digital data analyzer is used to display the binary form of each parallel bit word, and to decode and display the engineering and numeric data contained therein. The order of a certain field of bits of each word representing a word label is reversed in the shift register to enable direct decoding of the label by the data analyzer.

Abstract: A computer system based on a symbol-correcting code. The code words consist of a number of code symbols. In the normal operating mode of the error correction members, correction is possible of all errors which are either limited to one code symbol or which concern only two arbitrarily situated code bits. During operation in the erasure mode, a predetermined code symbol within the code word is not taken into account; therefore, it may contain an arbitrary, unknown error. An error can be corrected which concerns only one arbitrarily situated code bit. In the selection mode, two predetermined code symbols within the code word are not taken into account. The data words can be reconstructed from the others. The mode is controlled by the content of the mode register. The mode register is controlled by the output signals of syndrome generators.

Abstract: It is efficient to detect a data error, which is produced in a packet switching network, in a range between final users of data. A packet including data for detecting a data error is formed for a data unit made up of a series of data packets sent to a packet mode terminal, and send to the packet mode terminal. A data error is detected by the data for detecting a data error each time the above-mentioned series of data packets are received.

Abstract: A method and apparatus for correcting single bit errors in data stored in a first memory includes a dynamic shift register for dividing data by a polynomial during the time the data is being written into the first memory resulting in the generation of a remainder which is stored in a second memory. When reading the data from the first memory, the data is again divided by the same polynomial. The remainder generated by the second division is compared with the remainder stored in the second memory. If the remainders do not match, indicating an error was introduced into the data during storage or retrieval of the data in the first memory, the remainder stored in the second memory is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data located in the second memory.

Abstract: A system for testing digital circuit units at the design speed of the circuit. A first memory stores a minimized set of optimum generated predetermined test patterns for application to a unit under test. A second memory stores expected signature patterns corresponding to signature patterns that are derived from the unit under test in response to the predetermined test patterns when the unit under test is functioning properly. A signature analyzer derives signature patterns from a unit under test in response to the application of the test patterns to the unit. A comparator compares the derived signature patterns with the expected signature patterns and provides an indication of the results of the comparison.

Abstract: To recognize change in the storage characteristics of programmable memory elements, particularly EPROMs, the memory content of an addressed memory element or cell is read out, the first time, at normal design voltage level; the data so read are then again read out at a changed voltage level, for example at a higher or lower read-out voltage, or higher or lower operating voltage of the EPROM, and compared. If the data do not match, the particular memory cell will have the tendency to become defective due to loss or accumulation of charge carriers in due course although, for some time yet, the specific memory cell will function satisfactorily. Detection of errors upon operation under changed voltage conditions provides early warning of failure of a cell.

Abstract: A circuit for use in an in-circuit digital tester for generating data bus and control line test signals to test the electrical performance properties of components in a circuit under test is disclosed. Certain components in a circuit under test, such as microprocessors, are bus oriented devices which perform their functions in predetermined cycles. These cycles have been divided up into control sequences of control signals. Sequences of data signals are also generated. Each test pin in the bed of nails test fixture has a digital test signal generator associated therewith. The present invention operates to program each test signal generator with digital test signal generating data to produce the control and data sequences required to test a device under test during a test cycle. These predetermined sequences in control and data sequences are specified by a sequence in starting addresses of the programmable memory locations containing the selected control and data sequences to be generated.

Abstract: A checking apparatus for a copier includes check drive circuits having functions indentical to that of load driving circuits normally operated by a controller. The load driving circuits are bypassed in the check mode so that the loads are selectively operated by the check drive circuits, to test the output of a microprocessor or like device serving as a controller.

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N.

Abstract: A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers are used to store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provide a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data.

Abstract: A system having a plurality of redundant channels operating in tight synchronism wherein input information received in one or more of said channels is distributed to all the other channels. The received information in each channel is retransmitted to suitable voter circuitry in each channel so as to provide one or more voted outputs in each channel based on the distributed and retransmitted information from all the channels. The voted outputs from all unfailed channels are substantially identical and the voted output from a failed channel will not be identical to that of the unfailed channels.

Abstract: A large scale sequential integrated circuit is made amenable to scan design testing by the inclusion of special multiplexing and storage circuits which respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied the clock pulses which are used to control the storage elements and which, in such operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to such conditions.

Abstract: A test system and method for comparatively analyzing complex signals especially those composed of combinations of pulsed signals related to the operational status of apparatus whose operational status is to be determined, is disclosed. In the preferred embodiment a probe, preferably a capacitive probe, is utilized to sense the electric field generated by electrical apparatus. The output signal of the probe is periodically sampled to generate an array of digital signals. This array is processed using Walsh transformations to generate a reference Walsh transform. A second data base is then generated by similarly sampling the electric field generated by an apparatus whose operational status is to be determined. The second data base is then processed to generate a comparison Walsh transform. The operational status of the apparatus whose operational status is to be determined, is then determined by comparing these Walsh transforms.

Abstract: A microwave oven is disclosed as a typical appliance controlled by a microprocessor device. The oven has an LED digital display, a number of indicator LED's, and a capacitive touch keyboard, along with circuits for controlling a magnetron, a broiler unit, and a blower. A "self-test" feature causes the system to sequence through test routines whereby all LED's are lighted in a set order, each digit of the display counts up from 0 through 9, keyboard inputs entered are displayed as a code, and the magnetron and broiler are turned on.