Patents Examined by Mark V. Prenty
  • Patent number: 7267998
    Abstract: A magnetic memory device comprises a plurality of magneto-resistance effect elements arranged in a matrix form. The each of a plurality of magneto-resistance effect elements have a pattern shape which substantially internally touches an ellipse having major and minor axes of the magneto-resistance effect element as major and minor axes thereof and a pitch between the adjacent magneto-resistance effect elements in a direction of the major axis is longer than that in a direction of the minor axis.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Patent number: 7265447
    Abstract: Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Horng-Huei Tseng, Syun-Ming Jang, Chenming Hu
  • Patent number: 7265415
    Abstract: In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: September 4, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Praveen Muraleedharan Shenoy, Christopher Boguslaw Kocon
  • Patent number: 7265399
    Abstract: High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 4, 2007
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Jason Henning
  • Patent number: 7259463
    Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 21, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Jen Huang, Minghsing Tsai, Shau-Lin Shue, Hung-Wen Su, Ting-Chu Ko
  • Patent number: 7253475
    Abstract: Transistor cells (2) of a power transistor component are in each case provided with a gate conductor structure that forms a gate electrode (52) in sections and is connected via a gate cell terminal (43) to a gate wiring line (81) led to a gate terminal (44) of the power transistor component (1). The gate conductor structure (5) has a desired fusible section (51) with an increased resistance, which is arranged within a cavity. The resistance of the desired fusible section (51) can be set in such a way that, in the event of a current loading of the magnitude of a value that is typical of a defective gate dielectric (41), the gate conductor section (5) is interrupted in the desired fusible section (51) and the gate electrode (52) is disconnected from the gate wiring line (81). The power transistor component can be produced with high yield and has a smaller number of failures during application operation.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies AG
    Inventor: Carsten Schäffer
  • Patent number: 7253449
    Abstract: A light source module for a light emitting diode (LED) is provided. In the present invention, a common printed circuit board (PCB) is utilized to provide electric current and isolated from the heat dissipation mechanism, and the thermal conductive element, protruding from the LED package structure, is connected to another thermal conductive element to dissipate out the internal heat.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: August 7, 2007
    Assignee: AU Optronics Corporation
    Inventor: Meng-Chai Wu
  • Patent number: 7253497
    Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: August 7, 2007
    Assignee: LSI Corporation
    Inventors: Hemanshu D. Bhatt, Jan Fure, Derryl D. J. Allman
  • Patent number: 7244970
    Abstract: A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: July 17, 2007
    Assignee: Tyco Electronics Corporation
    Inventors: Adrian I. Cogan, Jin Qiu, Richard A. Blanchard
  • Patent number: 7242027
    Abstract: There is provided a light emitting and image sensing device for a scene. The light emitting and image sensing device is formed in a semiconductor substrate and comprises a photoemitter means for illuminating the scene with light, and a photosensor means for sensing an image of the scene. The photosensor means is responsive to incident light from the scene. In another embodiment of the present invention there is provided a light emitting and image sensing device for a scene. The light emitting and image sensing device includes a photosensor means for sensing the image of the scene, the photosensor means is formed in a first semiconductor substrate and is responsive to incident light from the scene, and a photoemitter means for illuminating the scene with light, the photoemitter means is formed in a second semiconductor substrate. The second semiconductor substrate is attached to the first semiconductor substrate.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: July 10, 2007
    Inventor: Paul Steven Schranz
  • Patent number: 7235845
    Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: June 26, 2007
    Assignee: Ciclon Semiconductor Device Corp.
    Inventors: Shuming Xu, Jacek Korec
  • Patent number: 7235811
    Abstract: A system and method are provided for reducing film surface protrusions in the fabrication of LILAC films. The method comprises: forming an amorphous film with a first thickness; annealing the film using a LILAC process, with beamlets having a width in the range of 3 to 10 microns; in response to annealing, forming protrusions on the film surface; optionally oxidizing the film surface; thinning the film; and, in response to thinning the film, smoothing the film surface. Typically, the film surface is smoothed to a surface flatness of 300 ?, or less. In some aspects of the method, oxidizing the film surface includes oxidizing the film surface to a depth. Then, thinning the film includes thinning the film to a third thickness equal to the first thickness minus the depth.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 26, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark A. Crowder, Apostolos T. Voutsas, Masahiro Adachi
  • Patent number: 7235826
    Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: June 26, 2007
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Patent number: 7233044
    Abstract: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 19, 2007
    Assignee: Atmel Germany GmbH
    Inventor: Volker Dudek
  • Patent number: 7230276
    Abstract: Provided is a semiconductor optical device having a current-confined structure. The device includes a first semiconductor layer of a first conductivity type which is formed on a semiconductor substrate and includes one or more material layers, a second semiconductor layer which is formed on the first semiconductor layer and includes one or more material layers, and a third semiconductor layer of a second conductivity type which is formed on the second semiconductor layer and includes one or more material layers. One or more layers among the first semiconductor layer, the second semiconductor, and the third semiconductor layer have a mesa structure. A lateral portion of at least one of the material layers constituting the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is recessed, and the recess is partially or wholly filled with an oxide layer, a nitride layer or a combination of them.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: June 12, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Woo Song, O Kyun Kwon, Won Seok Han, Sang Hee Park, Jong Hee Kim, Jae Heon Shin, Young Gu Ju
  • Patent number: 7227241
    Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: June 5, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Christoph Dirnecker, Jeffrey Babcock, Scott Balster
  • Patent number: 7227232
    Abstract: A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory cells have a second channel conductivity so that they are enhanced-mode MOS transistors. In the contactless Mask ROM, a memory cell shares two diffusions with two adjacent memory cells that are aligned with the memory cell along a first direction.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: June 5, 2007
    Assignee: Solid State System Co., Ltd.
    Inventors: Jhyy-Cheng Liou, Chin-Hsi Lin
  • Patent number: 7220992
    Abstract: A thin film transistor array panel is provided, which includes: a substrate; a plurality of first signal lines formed on the substrate; a plurality of second signal lines intersecting, and insulated from, the first signal lines; a plurality of pixel electrodes formed in intersection areas of the first and second signal lines; a plurality of first thin film transistors electrically connected to the first signal lines, the second signal lines, and the pixel electrodes; a plurality of buffer electrodes capacitively coupled to the pixel electrodes and located at a boundary of the intersection areas; and a plurality of second thin film transistors electrically connected to the buffer electrodes and the first signal lines, wherein the first signal lines are connected to the pixel electrodes of a previous row.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: May 22, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Lae Kim, Byeong-Seob Ban, So-Youn Park, Joon-Hak Oh
  • Patent number: 7214963
    Abstract: A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: May 8, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Gil Choi, Young-Ho Suh
  • Patent number: 7214974
    Abstract: An image sensor includes a substrate region of a first conductivity type, a photodiode region of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located at a surface of the substrate and over the photodiode region, and a transfer gate located over the surface of the substrate adjacent the HAD region. The image sensor further includes a first channel region of the first conductivity type located in the substrate and aligned below the transfer gate, a second channel region of the second conductivity type located in the substrate between said transfer gate and the first channel region, and an floating diffusion region which is located in the substrate and which electrically contacts the second channel region.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: May 8, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jongcheol Shin