Patents Examined by Mark V. Prenty
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Patent number: 11177451Abstract: An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.Type: GrantFiled: September 30, 2020Date of Patent: November 16, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Seo, Shunpei Yamazaki, Takahiro Ishisone
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Patent number: 11171234Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: GrantFiled: August 6, 2020Date of Patent: November 9, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
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Patent number: 11164972Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.Type: GrantFiled: December 23, 2019Date of Patent: November 2, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
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Patent number: 11152566Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.Type: GrantFiled: December 10, 2019Date of Patent: October 19, 2021Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Bo-Lun Wu, Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Patent number: 11145546Abstract: The present invention relates to a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, an insulating stacked structure and a first conductive layer. The gate structure is disposed on the substrate, and the insulating stacked structure covers the gate structure and the substrate to define a first opening thereinto expose a portion of the gate structure and a portion of the substrate. The first conductive layer covers surfaces of the first opening to directly contact the portion of the substrate and the portion of the gate structure, with the first conductive layer including two outer extension wings on a top surface of the insulating stacked structure.Type: GrantFiled: April 21, 2020Date of Patent: October 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Wu Wan, Tien-Hsiang Cheng, Kun-Hsuan Chung
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Patent number: 11145757Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.Type: GrantFiled: December 13, 2019Date of Patent: October 12, 2021Inventors: Young Chai Jung, Seon Bae Kim, Seung Hyun Song
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Patent number: 11133309Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.Type: GrantFiled: May 23, 2019Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
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Patent number: 11127640Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.Type: GrantFiled: February 19, 2020Date of Patent: September 21, 2021Inventor: Yeon-Cheol Heo
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Patent number: 11127848Abstract: A semiconductor structure includes a substrate structure having a plurality of first trenches extending in a first direction, a nucleation layer disposed on the substrate structure, a compound semiconductor layer disposed on the nucleation layer, a gate disposed on the compound semiconductor layer, and a source and a drain disposed on the compound semiconductor layer and at opposite sides of the gate.Type: GrantFiled: November 29, 2019Date of Patent: September 21, 2021Assignee: Vanguard International Semiconductor CorporationInventor: Chih-Yen Chen
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Patent number: 11114489Abstract: An image sensor for electrons or short-wavelength light includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. The circuit elements are connected by metal interconnects comprising a refractory metal. An anti-reflection or protective layer may be formed on top of the pure boron layer. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor.Type: GrantFiled: May 23, 2019Date of Patent: September 7, 2021Assignees: KLA-Tencor Corporation, Hamamatsu Photonics K.K.Inventors: Yung-Ho Alex Chuang, Jingjing Zhang, John Fielden, David L. Brown, Masaharu Muramatsu, Yasuhito Yoneta, Shinya Otsuka
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Patent number: 11107915Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.Type: GrantFiled: December 17, 2020Date of Patent: August 31, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Chie Fujioka, Hiroshi Yoshida, Yoshihiro Matsushima, Hideki Mizuhara, Masao Hamasaki, Mitsuaki Sakamoto
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Patent number: 11075208Abstract: An IC is provided. The IC includes a plurality of first cells arranged in a column of a first array, and a plurality of second cells arranged in a column of a second array. P-type fin field-effect transistors of the plurality of first cells share a first semiconductor fin including silicon germanium. P-type FinFETs of two adjacent second cells share a second semiconductor fin including Si. The first array is separated from the second array. A length of the second semiconductor fin is shorter than a length of the first semiconductor fin.Type: GrantFiled: October 16, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventor: Jhon-Jhy Liaw
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Patent number: 11063158Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.Type: GrantFiled: December 16, 2019Date of Patent: July 13, 2021Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lanxiang Wang, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
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Patent number: 11063049Abstract: A semiconductor memory device includes a substrate with a drain and a source; a gate structure, disposed on the substrate between the drain and the source; a first dielectric, disposed on the substrate, covering the gate structure; a second dielectric disposed on the first dielectric; a plug having a first part in the first dielectric and a second part in the second dielectric, wherein the first part is in contact with the source of the substrate; a storage node landing pad, covering the second part of the plug and covered by the second dielectric; a bit line disposed on the second dielectric and connected to the drain of the substrate; a third dielectric disposed on the bit line; and a storage node, disposed on the third dielectric, contacting the storage node landing pad through the second dielectric and the third dielectric.Type: GrantFiled: May 23, 2019Date of Patent: July 13, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ping Hsu
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Patent number: 11063032Abstract: Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures.Type: GrantFiled: December 19, 2019Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Jhon Jhy Liaw
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Patent number: 11049773Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.Type: GrantFiled: September 30, 2016Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Gilbert Dewey, Matthew V. Metz, Sean T. Ma, Cheng-Ying Huang, Tahir Ghani, Anand S. Murthy, Harold W. Kennel, Nicholas G. Minutillo, Jack T. Kavalieros, Willy Rachmady
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Patent number: 11050021Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a dielectric layer over the bottom electrode layer. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the dielectric layer and patterning the bottom electrode layer, the dielectric layer, and the top electrode layer to form a dielectric structure between a bottom electrode and a top electrode. The method for manufacturing a semiconductor structure further includes etching the bottom electrode from a sidewall of the bottom electrode to partially expose a bottom surface of the dielectric structure.Type: GrantFiled: November 8, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chern-Yow Hsu, Fu-Ting Sung, Shih-Chang Liu
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Patent number: 11037829Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.Type: GrantFiled: July 2, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Hyun Lee, Jeong Yun Lee, Seung Ju Park, Geum Jung Seong, Young Mook Oh, Seung Soo Hong
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Patent number: 11031487Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.Type: GrantFiled: December 3, 2019Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Andrew W. Yeoh, Tahir Ghani, Atul Madhavan, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 11031426Abstract: An image sensor includes a substrate, a grid isolation structure, and a color filter. The substrate has a light-sensitive element therein. The grid isolation structure is above the substrate and includes a reflective layer, a first dielectric layer above the reflective layer, and a second dielectric layer above the first dielectric layer. The color filter is above the light-sensitive element and is surrounded by the grid isolation structure.Type: GrantFiled: November 18, 2019Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Wei Cheng, Yin-Chieh Huang, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang