Patents Examined by Mark V. Prenty
  • Patent number: 7183583
    Abstract: A method for fabricating GaN-based LED is provided. The method first forms a first contact spreading metallic layer on top of the texturing surface of the p-type ohmic contact layer. The method then forms a second and a third contact spreading metallic layers on top of the first contact spreading layer. The p-type transparent metallic conductive layer composed of the three contact spreading metallic layers, after undergoing an alloying process within an oxygenic or nitrogenous environment under a high temperature, would have a superior conductivity. The p-type transparent metallic conductive layer could enhance the lateral contact uniformity between the p-type metallic electrode and the p-type ohmic contact layer, so as to avoid the localized light emission resulted from the uneven distribution of the second contact spreading metallic layer within the third contact spreading metallic layer. The GaN-based LED's working voltage and external quantum efficiency are also significantly improved.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 27, 2007
    Assignee: Super Nova Optoelectronics Corporation
    Inventors: Mu-Jen Lai, Schang-Jing Hon
  • Patent number: 7183621
    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: February 27, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, James G. Deak
  • Patent number: 7183639
    Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: February 27, 2007
    Assignees: Casio Computer Co., Ltd., CMK Corporation
    Inventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
  • Patent number: 7183586
    Abstract: A nitride semiconductor light emitting element is provided with: a substrate 11 having a pair of main surfaces that face each other; a nitride semiconductor layer of a first conductivity type layered on one of the main surfaces of substrate 11; a nitride semiconductor layer of a second conductivity type layered on the nitride semiconductor layer of the first conductivity type; an active layer 14 formed between the nitride semiconductor layer of the first conductivity type and the nitride semiconductor layer of the second conductivity type; and a reflective layer 16 formed on the nitride semiconductor layer of the second conductivity type for reflecting light from active layer 14 toward the nitride semiconductor layer of the second conductivity type. This nitride semiconductor light emitting element can be mounted on a circuit board, with the other main surface of the above described substrate 11 being used as the main light emitting surface.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: February 27, 2007
    Assignee: Nichia Corporation
    Inventors: Takashi Ichihara, Daisuke Sanga, Takeshi Kususe, Takao Yamada
  • Patent number: 7183628
    Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Stephen S. Furkay, Jeffrey B. Johnson, Robert M. Rassel, David C. Sheridan
  • Patent number: 7183569
    Abstract: A gallium nitride semiconductor laser device has an active layer (6) made of a nitride semiconductor containing at least indium and gallium between an n-type cladding layer (5) and a p-type cladding layer (9). The active layer (6) is composed of two quantum well layers (14) and a barrier layer (15) interposed between the quantum well layers, and constitutes an oscillating section of the semiconductor laser device. The quantum well layers (14) and the barrier layer (15) have thicknesses of, preferably, 10 nm or less. In this semiconductor laser device, electrons and holes can be uniformly distributed in the two quantum well layers (14). In addition, electrons and holes are effectively injected into the quantum well layers from which electrons and holes have already been disappeared by recombination. Consequently, the semiconductor laser device has an excellent laser oscillation characteristic.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: February 27, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiyuki Okumura
  • Patent number: 7180133
    Abstract: In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: February 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski, Philipp Lindorfer
  • Patent number: 7180138
    Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: February 20, 2007
    Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun Park
    Inventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
  • Patent number: 7173292
    Abstract: In a field effect transistor having a quantum well is provided by a primary conduction channel, at least one secondary conduction channel immediately adjacent and in contact with the primary channel has an effect bandgap greater than the effective bandgap of the primary channel, and the modulus of the difference between the impact ionisation threshold IIT of the primary channel and the effective conduction band offset (the height of the step) between the primary and secondary channels being no more than 0.5 Eg (effective), or (alternatively) no more than 0.4 eV. Higher energy carriers which might otherwise cause impact ionization leading to runaway are thus diverted into the secondary channel allowing the device to run faster at increased voltages and/or to exhibit much greater resistance to runaway. The primary channel is prefereably of low bandgap material, for example InSb, InAs, InAs1-y, In1-xGaxAs.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: February 6, 2007
    Assignee: Qinetiq Limited
    Inventor: Timothy Jonathan Phillips
  • Patent number: 7173301
    Abstract: The inventive ferroelectric memory device includes: a semiconductor substrate providing elements of a transistor; a first inter-layer insulating layer formed on the semiconductor substrate; a storage node contact connected to elements of the transistor by passing through the first inter-layer insulating layer; a barrier layer contacting simultaneously to the storage node contact and the first inter-layer insulating layer; a lower electrode having a space for isolating the first inter-layer insulating layer and being formed on the barrier layer; a glue layer being formed on the first inter-layer insulating layer and encompassing lateral sides of the lower electrode as filling the space; a second inter-layer insulating layer exposing a surface of the lower electrode and encompassing the glue layer; a ferroelectric layer formed on the glue layer including the second inter-layer insulating layer; and an upper electrode formed on the ferroelectric layer.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: February 6, 2007
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Eun-Seok Choi, Seung-Jin Yeom
  • Patent number: 7170180
    Abstract: Methods and systems for current sharing between power semiconductors in an assembly are provided. The power semiconductor assembly includes a plurality of power semiconductors, each comprising at least one output conductor, the plurality of output conductors are electrically coupled together in parallel, an output bus network configured to transpose the output conductors such that magnetic fields causing a current output imbalance between the plurality of power semiconductors are substantially canceled.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: January 30, 2007
    Assignee: General Electric Company
    Inventor: Robert Gregory Wagoner
  • Patent number: 7170100
    Abstract: Light-emitting devices, and related components, processes, systems and methods are disclosed.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: January 30, 2007
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Paul Panaccione, Robert F. Karlicek, Jr., Michael Lim, Elefterios Lidorikis, Jo A. Venezia, Christian Hoepfner
  • Patent number: 7166926
    Abstract: The method of producing a semiconductor device in which chips are resin-molded, including steps of: preparing frames having front and back surfaces and die pads; preparing an insulation resin sheet having a first and a second surfaces; preparing a resin-sealing metal mold having cap pins; mounting the resin sheet inside the resin-sealing metal mold in such a manner that the second surface of the resin sheet contacts an inner bottom surface of the resin-sealing metal mold; mounting power chips on the surfaces of the die pads; positioning the frames on the first surface of the resin sheet in such a manner that the back surfaces of the die pads contact the first surface of the resin sheet; pressing the die pads toward the resin sheet using the cap pins and fixing the die pads; injecting a sealing resin in the resin-sealing metal mold and hardening the sealing resin; and removing the semiconductor device in which the power chips are molded with the sealing resin out from the resin-sealing metal mold.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: January 23, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Hayashi, Hisashi Kawafuji, Tatsuyuki Takeshita, Nobuhito Funakoshi, Hiroyuki Ozaki
  • Patent number: 7166916
    Abstract: A semiconductor integrated circuit is so structured that a first insulating layer is formed on a surface of a semiconductor chip and a second insulating layer covers an entire region of the surface of the semiconductor chip. Via apertures made to the second insulating layer, an electrical connection configuration is formed from above the second insulating layer by using gold wires. Then, an electronic component is mounted on the second insulating layer. By arranging as such, the electronic component is mounted on the semiconductor chip in advance. Therefore, it is possible to further reduce mounting space on a printed-wiring board and also possible to make is easy to attain one-packaged IC.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: January 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Akamatsu, Masanori Inamori
  • Patent number: 7164176
    Abstract: An integrated circuit comprises a first source, a first drain and a first gate that is arranged between the first source and the first drain. A first body is arranged in the first source. A second gate is arranged between the first source and a second drain. The first body includes a body contact tap. The first and second gates are arranged farther apart adjacent to said body contact tap than in areas that are not adjacent to said body contact tap An edge of the first body is substantially aligned with the first gate.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: January 16, 2007
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 7161194
    Abstract: Field effect transistors having a power density of greater than 25 W/mm when operated at a frequency of at least 4 GHz are provided. The power density may be at least 30 W/mm when operated at 4 GHz. The power density of at least 30 W/mm may be provided at a drain voltage of 120 V. Transistors with a power density of at least 30 W/mm when operated at 8 GHz are also provided. The power density of at least 30 W/mm may be provided at a drain voltage of 120 V. Field effect transistors having a power density of greater than 20 W/mm when operated at a frequency of at least 10 GHz are also provided. Field effect transistors having a power density of at least 2.5 W/mm and a two tone linearity of at least ?30 dBc of third order intermodulation distortion at a center frequency of at least 4 GHz and a power added efficiency (PAE) of at least 40% are also provided.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 9, 2007
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Yifeng Wu, Adam William Saxler
  • Patent number: 7157758
    Abstract: A solid-state image sensing device is provided. In the device, a first floating p-type well and a second floating p-type well are disposed so as to overlap each other and are respectively provided in a light-receiving area and the area of a field effect transistor for light signal detection. A circular gate electrode is disposed so as to cover the overlapping section of the first floating p-type well with the second floating p-type well and is formed on an n-type channel doped layer.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: January 2, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akira Mizuguchi
  • Patent number: 7157793
    Abstract: Thermal spreading resistance, associated with small geometry electronic features that generate heat on a semiconductor, may be reduced through the addition of a thermally conductive fluid. For example, a dielectric fluid may be used within a volume between a semiconductor package and the semiconductor substrate. Therefore, direct thermal cooling may be employed to reduce the thermal spreading resistance often encountered in MMIC power amplifier devices. Furthermore, exemplary methods to achieve this sealing are described herein.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: January 2, 2007
    Assignee: U.S. Monolithics, L.L.C.
    Inventors: Richard S. Torkington, Jon Filreis, Kenneth V. Buer
  • Patent number: 7148504
    Abstract: One of aspects of the present invention is to provide a semiconductor device, which includes an insulating substrate, and a semiconductor chip mounted on the insulating substrate. The semiconductor chip has a chip electrode thereon. The semiconductor device also includes a first terminal electrically connected with the chip electrode through a first metal wire, and a second terminal electrically connected with the chip electrode through a second metal wire that is more likely to be disconnected than the first metal wire. A signal of disconnection of the second metal wire is output at the second terminal.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: December 12, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Junji Yamada
  • Patent number: 7148557
    Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: December 12, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Manabu Yanagihara, Naohiro Tsurumi, Tsuyoshi Tanaka, Daisuke Ueda